PSoC6 bluetooth - hci_write fail UART is NOT initialized

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chwaitang
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First solution authored 25 sign-ins 10 replies posted

Hi All,

I get above error when I compiled my custom bluetooth code modify from Bluetooth_LE_CTS_Server. Compilation is ok but after I download into M4 cpu, I always get these errors (BLE Stack initialisation ok).

[722215] hci_write(): UART is NOT initialized
[722215] handle_hci_tx_command(): hci write failed (0xb7)
[726231] hci_write(): UART is NOT initialized
[726231] handle_hci_tx_command(): hci write failed (0xb7)

I do not encounter any error when running Bluetooth_LE_CTS_Server example. And I cannot find any difference in code initialisation steps between my custom program and that example. Can anyone advise? 

 

Also I have another question:

1)  I read about downloading bt firmware for L1V module in w_bt_firmware_controller.c. May I know the difference between Bluetooth_LE_CTS_Server example and this w_bt_firmware_controller.c. Where does the firmware in array inside w_bt_firmware_controller.c download to? And why is there a need for this bluetooth firmware compared with bluetooth functionalities provided by WICED_BLE library api?

My limited understanding of the above is the bluetooth firmware provided in w_bt_firmware_controller.c does not allow you to have access to CM0 or CM4 cpu if you are using this. And you can only communicate with the particular cpu (CM0 or CM4) which this firmware is downloaded via hci uart but the particular cpu cannot be used for user program. Is this correct? And w_bt_firmware_controller.c is meant for CM0 and not CM4. Is that correct?

Warm regards

CW

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BragadeeshV
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First question asked 1000 replies posted 750 replies posted

Hi @chwaitang ,

0x4021e00 is the Cy_result. This needs to be decoded using the following helper method

https://infineon.github.io/mtb-hal-cat1/html/group__group__result.html

The issue is coming from the UART HAL driver with error CYHAL_UART_RSLT_ERR_INVALID_PIN. This is the result of Cyhal_uart_init() in cybt_platform_hci_open(). This could mean one of the following:

1. You have used the UART pins for some other functionality (GPIO or some other HW block) and the HW reserve manager is preventing you from using these pins.

2. You have used the same SCB block for some other functionality. For example, P3.0 to P3.3 (Tx, rx, cts, rts) that connects wireless chip belongs to SCB2.  You need to ensure that you did not use SCB 2 for other functionalities such as I2C or SPI.  

Similar issue: https://community.infineon.com/t5/PSoC-6/hci-open-init-error-0x4021c00/td-p/332817 -> Here the customer used older version of HAL so the result code value might look different but it is the same issue.

Regards,
Bragadeesh

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BragadeeshV
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Hi @chwaitang ,

Could you please let us know if you are using any custom board or is it any of the development kits? Which wireless chip are you using?

Could you please list the changes you made to the original example or share your custom code for us to debug the issue?

1)  I read about downloading bt firmware for L1V module in w_bt_firmware_controller.c. May I know the difference between Bluetooth_LE_CTS_Server example and this w_bt_firmware_controller.c.

-> Internally, the Bluetooth_LE_CTS_Server will load the FW file to the combo chip to initialize the BT domain of the chip. You can find this file in the following path. For example

<src_dir>\mtb_shared\bluetooth-freertos\release-vx.y.z\firmware\COMPONENT_4343W\COMPONENT_MURATA-1DX\COMPONENT_HCI-UART

Where does the firmware in array inside w_bt_firmware_controller.c download to?

-> This FW file is a pre-built firmware and will be placed in the RAM of the wireless device.

And why is there a need for this bluetooth firmware compared with bluetooth functionalities provided by WICED_BLE library api?

-> The combo chip is used in hosted mode. This means that the PSoC 6 will run BT host level functions and the controller will perform the BT controller (Link layer + PHY ) functions. The firmware file will be loaded to the RAM of the combo chip and will contact the firmware patches and configures the bt domain of the chip.

My limited understanding of the above is the bluetooth firmware provided in w_bt_firmware_controller.c does not allow you to have access to CM0 or CM4 cpu if you are using this. And you can only communicate with the particular cpu (CM0 or CM4) which this firmware is downloaded via hci uart but the particular cpu cannot be used for user program. Is this correct? And w_bt_firmware_controller.c is meant for CM0 and not CM4. Is that correct?

-> This understanding is not correct. In the examples provided, the CM4 runs the BT host stack and it also performs the FW RAM download to the combo chip.

Regards,
Bragadeesh
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Hi BragadeeshV,

1) I am using PSoC62S2 Wi-Fi BT Pioneer Kit and attached toned down version of CM4 fw with only bsp peripheral and ble init. ble stack init passed and I have not send any ble commands or api calls (not transmitting anything via hci-uart) but keep getting following error via debug uart in while loop.

[6019] hci_write(): UART is NOT initialized
[6019] handle_hci_tx_command(): hci write failed (0xb7)

 

I intend to use both wi-fi and bluetooth concurrently (wifi for data post and bluetooth for device). My understanding is the ble and wifi stack on Combo chip will manage the radio protocol switching to make it appears concurrent so there's no need for user to switch between wifi and bluetooth api calls/init/de-init  but both wifi and bluetooth share same physical antenna on the pioneer kit. Is this correct?

 

2) I do not see any difference in the initialisation between my attached code and the Bluetooth LE CTS server.

In addition I have use device configurator to configure pre-defined GPIO pins P3.0 to P3.5 on PSoC6 for bluetooth to have same debug uart  GPIO settings, compiled and run the program but still same result. This is because I do not see any GPIO initialisation in bsp and ble init API.  Also I can only find the generated source for bluetooth in cycfg_bt_settings.c but assume this is for initialisation of bluetooth parameters and does not do the lower level IO initialisation. Where is this part of the initialisation done? 

Please advise.

Warm regards

CW

 

 

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BragadeeshV
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First question asked 1000 replies posted 750 replies posted

Hi @chwaitang ,

I intend to use both wi-fi and bluetooth concurrently (wifi for data post and bluetooth for device). My understanding is the ble and wifi stack on Combo chip will manage the radio protocol switching to make it appears concurrent so there's no need for user to switch between wifi and bluetooth api calls/init/de-init  but both wifi and bluetooth share same physical antenna on the pioneer kit. Is this correct?

-> Yes your understanding is correct. This is already taken care. WiFi uses SDIO interface and BT uses UART interface therefore the communication between the host and the controller can happen simultaneously for BT and WIFI.

In addition I have use device configurator to configure pre-defined GPIO pins P3.0 to P3.5 on PSoC6 for bluetooth to have same debug uart  GPIO settings, compiled and run the program but still same result. This is because I do not see any GPIO initialisation in bsp and ble init API.  Also I can only find the generated source for bluetooth in cycfg_bt_settings.c but assume this is for initialisation of bluetooth parameters and does not do the lower level IO initialisation. Where is this part of the initialisation done? 

-> This is not required since it is already taken care by the internal library (bluetooth-freertos). For your understanding, please check the function cybt_platform_hci_open() in the file cybt_platform_freertos.c  (mtb_shared\bluetooth-freertos\release-vx.y.z\platform\freertos)

It initializes the right pins for UART , BT REG ON pin and the sleep mode pins. The user only needs to call the functions cybt_platform_config_init() and wiced_bt_stack_init() from the application. Therefore, you need not perform any other initializatio in your application or in design.modus file.

Can you enable lower layer debugging messages by using the following API and please share the complete tera term message logs? Sample logs attached. Call this before cybt_platform_config_init().

cybt_platform_set_trace_level(CYBT_TRACE_ID_ALL, CYBT_TRACE_LEVEL_MAX);

Regards,
Bragadeesh
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chwaitang
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First solution authored 25 sign-ins 10 replies posted

Hi 

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chwaitang
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attached log

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chwaitang
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This is debug log after I remove all pin config for P3.0 to P3.5 in the device configurator since u say they are not needed. Notice the 

2] hci_open(): Init power pin failed (0x4020d01) has changed to

[502] hci_open(): init error (0x4021e00)

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BragadeeshV
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First question asked 1000 replies posted 750 replies posted

Hi @chwaitang ,

0x4021e00 is the Cy_result. This needs to be decoded using the following helper method

https://infineon.github.io/mtb-hal-cat1/html/group__group__result.html

The issue is coming from the UART HAL driver with error CYHAL_UART_RSLT_ERR_INVALID_PIN. This is the result of Cyhal_uart_init() in cybt_platform_hci_open(). This could mean one of the following:

1. You have used the UART pins for some other functionality (GPIO or some other HW block) and the HW reserve manager is preventing you from using these pins.

2. You have used the same SCB block for some other functionality. For example, P3.0 to P3.3 (Tx, rx, cts, rts) that connects wireless chip belongs to SCB2.  You need to ensure that you did not use SCB 2 for other functionalities such as I2C or SPI.  

Similar issue: https://community.infineon.com/t5/PSoC-6/hci-open-init-error-0x4021c00/td-p/332817 -> Here the customer used older version of HAL so the result code value might look different but it is the same issue.

Regards,
Bragadeesh
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Hi BragadeeshV,

Thanks! That helps

Warm regards

CW