PSoC6 SmartIO Code Example

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
SaKu_291986
Level 4
Level 4
10 replies posted 10 questions asked 5 solutions authored

This issue is with reference to mtb example psoc6 smartio sgpio target.

The SmartIO configurator does not carry the configuration applied to SmartIO during runtime. Can the run time configuration be updated, so that I need not decode the code in sgpio_target.c to understand and verify the SmartIO?

Best regards,

Sampath Kumar

0 Likes
1 Solution
lock attach
Attachments are accessible only for community members.
RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

Yes, we decided to load the Smart I/O configuration during the SGPIO initialization. This makes easier to use the SGPIO library, so user only needs to worry about the SPI and Smart I/O connections in the device configurator.

Still, we could follow your suggestion, so it is easy to visualize what the SGPIO library does.

I'm attaching the design.modus with such configuration for the TARGET-CY8CKIT-062-WIFI-BT. You can open with the ModusToolbox Device Configurator.

View solution in original post

0 Likes
3 Replies
lock attach
Attachments are accessible only for community members.
RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

Yes, we decided to load the Smart I/O configuration during the SGPIO initialization. This makes easier to use the SGPIO library, so user only needs to worry about the SPI and Smart I/O connections in the device configurator.

Still, we could follow your suggestion, so it is easy to visualize what the SGPIO library does.

I'm attaching the design.modus with such configuration for the TARGET-CY8CKIT-062-WIFI-BT. You can open with the ModusToolbox Device Configurator.

0 Likes

Thank you very much for the SmartIO configurator update. I managed to get the digital equations for SmartIO.

Combinatorial

LUT0:

CHIP_SPI_MOSI = PIN_SPI_MOSI

LUT2:

CHIP_SPI_CLK = PIN_SPI_CLK

Clock gated with SPI SGPIO Target master clock

LUT1:

PIN_SPI_MISO = CHIP_SPI_MISO

LUT4

SPI_CLK_DELAYED1 = CHIP_SPI_CLK

LUT5

SPI_CLK_FALLING = !CHIP_SPI_CLK & SPI_CLK_DELAYED1

LUT3

CHIP_SPI_SS = LUT6 | (!LUT6 & SPI_CLK_FALLING & PIN_SPI_SS)

LUT6

LUT6 = CHIP_SPI_SS & !DU_OUT

DU

DU.RST = SPI_CLK_FALLING

DU.EN = TRUE

Can you kindly let me know if the above equations are OK? Are we trying to get the chip spi_ss to go high for a few clocks after an SPI_CLK falling edge while the pin SPI_SS is high? The data unit seems to go high after 254 clocks, so I am unable to relate the equations.

Best regards,

Sampath Kumar

0 Likes
RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

We want the SPI_SS work as the SGPIO SLOAD signal. The SLOAD only asserts for one cycle every frame, while the SPI_SS needs to be asserted all the time during the transfer. 

So the idea is to assert the SPI_SS when the SLOAD is first detect and keep asserted all the time. The DU works as a timeout mechanism, if the SLOAD stops asserting for a frame. If that's the case, we de-assert the SPI_SS.

0 Likes