PSoC 6 Dual Core Debugging

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CoreyW_81
Employee
Employee
50 sign-ins 50 replies posted 25 replies posted

Is there a guide to Dual Core Debugging for the PSOC 6 within Keil uVision?

Specifically, customer needs to be debugging the CM4 and when a breakpoint is hit on the CM4, he would like the CM0+ to stop as well.

I think there are bits that need to be set for the CTI and CTM, but we cannot find the documentation on how this is done.

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5 Replies
VenkataD_41
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi,

Please go through section 3. Debug µVision Projects in page number 24 of the following application note.

https://www.cypress.com/file/385711/download

Hope this helps !

Thanks

Ganesh

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Ganesh - This is great material but does not address the question about the right settings to allow a breakpoint on one processor to break the other, or not.  How is this accomplished in uVision?

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Stopping the CM0+ core when attaching to the CM4 can prevent system calls from executing and result in failure of clocks/pin/interrupt initialization in the CM0+ application. Can you please let me know why you would require such debug functionality?

For information on how to enable dual-core debugging on Keil uVision, you can refer this AN: http://www.keil.com/appnotes/files/apnt_318.pdf

Regards,

Dheeraj

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Dheeraj - From the customer:

I don't understand. I need to debug the system with two cores working simultaneously. I do understand that there are some limitations, what are they? "...clocks/pin/interrupt initialization in the CM0+ application". Is it during initialization only or what?

I totally do NOT understand the second part: I need to debug TWO cores and it seems to be a quite valid reason.

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Yes the requirement is valid. I understand your concerns. We currently do not have any document explaining this and I have passed this query to the internal software team for evaluation.

Thank you for your interest in Cypress Products.

Regards,
Dheeraj

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