PSOC62: resetting only 1 core; freezing the GPIOs during reset of that core

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LuRo_4811501
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Hi,

we are developing an application with the CY8C6247BZI-D54 and I couldn’t find a clear answer for the following, or I found contradictory information:

1. Can we reset ONLY 1 core and keep the other one operating in normal power mode? If yes, which core is possible to reset alone, CM0+ or CM4?

2. Assuming it is possible to reset only 1 core, is it possible to “freeze” the GPIOs (or at least a few GPIOs) such that they keep the state while that core is reset?

Thank you

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DheerajK_81
Moderator
Moderator
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First comment on KBA First comment on blog 5 questions asked

Hello,

Answers inline.

1. Can we reset ONLY 1 core and keep the other one operating in normal power mode? If yes, which core is possible to reset alone, CM0+ or CM4?

You can cause a software reset of the CM4 core from CM0p by calling the API Cy_SysLib_SoftResetCM4.  Note that this should only be called when CM4 is in DeepSleep mode. Refer to the PDL documentation to learn more about this.

Resetting CM0p causes the CM4 also to be reset because it enables the CM4 processor. Both the cores can cause a system reset by calling __NVIC_SystemReset().

2. Assuming it is possible to reset only 1 core, is it possible to “freeze” the GPIOs (or at least a few GPIOs) such that they keep the state while that core is reset?

No. If you issue a soft reset, all the states will be reset. The default state of the GPIO will be Analog High-Z. You could probably try putting the core to hibernate where the GPIO states are frozen if that helps. What is your requirement for maintaining the states?

The following document may be useful if you want to learn about Hibernate and other power mode options in the PSoC6: https://www.cypress.com/file/385936/download

Regards,

Dheeraj

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DheerajK_81
Moderator
Moderator
Moderator
First comment on KBA First comment on blog 5 questions asked

Hello,

Answers inline.

1. Can we reset ONLY 1 core and keep the other one operating in normal power mode? If yes, which core is possible to reset alone, CM0+ or CM4?

You can cause a software reset of the CM4 core from CM0p by calling the API Cy_SysLib_SoftResetCM4.  Note that this should only be called when CM4 is in DeepSleep mode. Refer to the PDL documentation to learn more about this.

Resetting CM0p causes the CM4 also to be reset because it enables the CM4 processor. Both the cores can cause a system reset by calling __NVIC_SystemReset().

2. Assuming it is possible to reset only 1 core, is it possible to “freeze” the GPIOs (or at least a few GPIOs) such that they keep the state while that core is reset?

No. If you issue a soft reset, all the states will be reset. The default state of the GPIO will be Analog High-Z. You could probably try putting the core to hibernate where the GPIO states are frozen if that helps. What is your requirement for maintaining the states?

The following document may be useful if you want to learn about Hibernate and other power mode options in the PSoC6: https://www.cypress.com/file/385936/download

Regards,

Dheeraj

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