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PSoC™ 6 Forum Discussions

azBlock1
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I am using CY8C6244AZI-S4D93 MCU with the above device configurator settings for clocking.

I have an external oscilator that is 12Mhz going into the EXTCLK of the system and being used as the source for both PLL and FLL. PLL is used to generate the main system clock.

My goal is to output a 15Mhz signal on the External Clock pin P0[5]. I have a PCB with this pin exposed and i have been using a 500MS/s logic analyzer to measure the frequency of this clock.

I have the FLL configured to generate a 60Mhz clock, and then using a /4 divider in the CLK_HF1 block the tool shows me that i get 15Mhz. However when i measure this on P0[5] i only get 3Mhz or 1/4th of my input EXTCLK. If i set the divider of CLK_HF1 to 1 i get the 12Mhz on the output, not the 60Mhz from the FLL. There is no configuration that seems to get me 15Mhz from the FLL on the CLK_HF1 output pin.

This seems to be a bug but im not sure where to look to figure it out since this is all the configurator tool.

Note: this is Device Configurator 4.0.0.748 and 3.0 tools.

 

Edit 1: After tons of debugging i found the issue. I used Cy_SysClk_FllGetConfiguration() in CM4 main and when i checked it the outputMode was set to CY_SYSCLK_FLLPLL_OUTPUT_INPUT which is bypassing the FLL. Eventually after jumping around a bunch the issue was "Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)" call in CM0 core. This disabled the FLL output along with a few other things. Taking that out got me my 15Mhz on pin  P0[5]

Posting here as an update in case someone runs into something like this in the future.

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Ekta
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After tons of debugging i found the issue. I used Cy_SysClk_FllGetConfiguration() in CM4 main and when i checked it the outputMode was set to CY_SYSCLK_FLLPLL_OUTPUT_INPUT which is bypassing the FLL. Eventually after jumping around a bunch the issue was "Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)" call in CM0 core. This disabled the FLL output along with a few other things. Taking that out got me my 15Mhz on pin  P0[5].

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Ekta
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250 solutions authored 100 likes received 250 sign-ins

After tons of debugging i found the issue. I used Cy_SysClk_FllGetConfiguration() in CM4 main and when i checked it the outputMode was set to CY_SYSCLK_FLLPLL_OUTPUT_INPUT which is bypassing the FLL. Eventually after jumping around a bunch the issue was "Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)" call in CM0 core. This disabled the FLL output along with a few other things. Taking that out got me my 15Mhz on pin  P0[5].

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