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yiru_1705901
Level 4
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First solution authored 25 replies posted 25 sign-ins

我的需求是 是类I2C通信,四个数据线公用一个时钟线,不是QSPI,四个数据线独立发送数据的,时钟大于等于20MHZ,用UDB可以实现吗? 

我使用的芯片是CY8C6247AZI-D54,有12个UDB, 我用IO口模拟的通信如附件。

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@yiru_1705901 ,

Attached is a PSoC Creator starter project.  The project will go through the Application Build stage (ie. TopDesign with no errors) but the main_cm4.c code is incomplete and will throw errors.   (You need to fill in the missing code.).

Here is the TopDesign that links ALL 3 SPI channels to one clock that can be enabled and disabled at the same time.  This should synchronize ALL SPI channels so that you can use one clock.

Len_CONSULTRON_0-1697988676767.png

The Clock_RGB has an _Enable() and _Disable() API call to start and stop the source clock to the SPIs.

Also, I use only one DMA channel.   You can use a separate DMA for each channel if you would prefer.  However, with 3 TDs for one channel, you can move 3 words of data from different memory regions with one DMA event.

Also note that the source clock is 80MHz and each of the SPI channels are only using 4x oversampling.   With these parameters, the SPI clock output is 20Mbps as desired.

Another note:  The project I supplied is for the CY8C6247BZI-D54 CPU.  The CY8C6247AZI-D54 you are targeting does not exist in my version of PSoC Creator.  This part may be an older part no longer supported by Infineon.   Consult with Infineon.

Len
"Engineering is an Art. The Art of Compromise."

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Vison_Zhang
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750 replies posted 250 sign-ins 250 solutions authored

如果你使用 Creator IDE, 可以参考帖子 https://community.infineon.com/t5/PSoC-6/How-can-I-instantiate-a-UDB-based-I2C-UART-Controller-with-... 我在里面上传了已经移植好的 PSOC6-UDB-I2C 组件库

 

如果使用 ModusToolBox IDE 的话,就要麻烦一些,因为 MTB 并没有办法直接使用 Creator  UDB 组件库,也没有开发对应的 UDB 工具,所以需要借助工具,将 UDB 设置转成 .c 的之后给 MTB 使用才可以,详细步骤和方法请参考 https://forum.onethinx.com/t/udb-porting-tool-export-the-udb-configuration-from-psoc-creator-to-modu... 

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不好意思   我没描述清除,我的需求是用PSOC6刷灯的(控制192*192个三色灯),一个时钟线和三个(RGB)颜色数据线,我用IO口模拟可以正常通信,但是速度太慢刷不过来,代码如附件,我用的是creator,  我这几天也在浏览UDB的资料,感觉是可以做的,但是不知道怎么下手,我对这方便不是很熟悉,还正在看UDB相关文档。 你们把I2C组件的UDB源码发我参考一下吗,或者可以加下你联系方式吗 ?

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更正一下,实际是一个时钟线和4个信号线,除了RGB三个颜色信号线还有一个命令信号线(固定值0x01),    每个信号线输出应该是需要一个UDB,我不知道时钟信号线需不需要UDB,如果时钟不需要,那就是4个UDB就可以实现这个功能,大哥方便帮我搞个,我这个功能比较简单 ,就是发送数据

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@yiru_1705901 ,

Can you use SPI instead of I2C?

If so, you do have to make sure that all the data (R, G and B) are loaded into the FIFO first then launch the SPI Tx to start.   Once started, you can use the CPU (if fast enough) or DMA to continue to load the continuous stream of RGB data.

Note: Since you are trying to use 1 clock, all data must be preloaded into the FIFO before the clock starts for each R, G and B transfer.

Len
"Engineering is an Art. The Art of Compromise."

Yea, I agree, I2C is not a good start point

Without considering designing customized components (which may be difficult for most customers), may I ask if your idea is to use 3 independent SPIs component  plus with DMA and Digital Logic to implement three synchronized serial signals?

I'm considering it may be easier to use a 3 shift register components plus with DMA + Digital Logic to achieve the same functionality.

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可以 ,能帮忙写个简单例程给我吗,非常感谢

 

 

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之前我也想过用SPI去实现,但是很难让3个spi 同时启动

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@yiru_1705901 ,

Attached is a PSoC Creator starter project.  The project will go through the Application Build stage (ie. TopDesign with no errors) but the main_cm4.c code is incomplete and will throw errors.   (You need to fill in the missing code.).

Here is the TopDesign that links ALL 3 SPI channels to one clock that can be enabled and disabled at the same time.  This should synchronize ALL SPI channels so that you can use one clock.

Len_CONSULTRON_0-1697988676767.png

The Clock_RGB has an _Enable() and _Disable() API call to start and stop the source clock to the SPIs.

Also, I use only one DMA channel.   You can use a separate DMA for each channel if you would prefer.  However, with 3 TDs for one channel, you can move 3 words of data from different memory regions with one DMA event.

Also note that the source clock is 80MHz and each of the SPI channels are only using 4x oversampling.   With these parameters, the SPI clock output is 20Mbps as desired.

Another note:  The project I supplied is for the CY8C6247BZI-D54 CPU.  The CY8C6247AZI-D54 you are targeting does not exist in my version of PSoC Creator.  This part may be an older part no longer supported by Infineon.   Consult with Infineon.

Len
"Engineering is an Art. The Art of Compromise."

非常感谢,我调试测试看看

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@Len_CONSULTRON @Vison_Zhang    通过控制spi时钟的开关 是可以让4个spi同步,但是spi速度只能达到15MHZ,再高就不同步了,我用逻辑分析仪抓取分析了一下,中间往后基本每16个时钟有个停顿,应该是CPU处理不过来了,随着SPI速度的提高,外设到DMA的请求也越频繁频繁,CPU处理能力不足,导致DMA按照优先级一个一个来,导致不同步 @Vison_Zhang  你给的方法也是同样的问题, 有什么方法能提高速度,

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yiru_1705901_0-1701335036631.png

这是测试波形 从中间开始 每16个时钟 会有个停顿,然后4个spi 就不同步了

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我更正一下,实际是一个时钟线和4个信号线,除了RGB三个颜色信号线还有一个命令信号线(固定值0x01),    每个信号线输出应该是需要一个UDB,我不知道时钟信号线需不需要UDB,如果时钟不需要,那就是4个UDB就可以实现这个功能,大哥方便帮我搞个,我这个功能比较简单 ,就是发送数据

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我现在的大致思路是,4个数据线公用一个时钟线,每个UDB 判断datapath输出FIFO不为满时,不断填充数据,通过移位寄存器发送出去,数据发完后判断FIFO为空,进行其他处理 

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Vison_Zhang
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750 replies posted 250 sign-ins 250 solutions authored

@yiru_1705901 我汇总一下目前的思路。首先我不建议你基于 UDB 去设计定制化模块,虽然这条路肯定是可行的,但是需要你前期要研读很多文档,会比较麻烦。Len 和我的思路都是复用目前已有的硬件模块来实现设计,无论是使用 SPI 模块还是 level shift 模块,都是基于其已包含 FIFO 部分,相比较而言  SPI 更好一些,因为其  FIFO 有一定的深度,更适合 buffer 大量数据的传输。

至于三路 SPI 的同步,我认为这个容易解决。附件工程中的截图部分,实现了一个将 1500+ bytes 数据发送出的功能,其中首次发送的触发可以利用 Control Register 提供一个 trigger 来实现,如果对三个 mSPI 适配三个独立的 DMA 并且使用同一个 Control Register 提供 trigger 信号,那么实现三路信号的同步传输是可以的。

Vison_Zhang_0-1698022961661.png

 

如何使用 PSoC6 中的 DMA, 你可以参考我的例程,也可以阅读 AN AN228753 - PSoC™ 6 MCU usage of Direct Memory Access (DMA) 

 

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@Vison_Zhang ,

I've looked at your project.   I see how you are trying to load all 3 words into 3 SPI FIFOs nearly at the same time using one DMA event.

However, if you have 3 separate SPIs I don't see how you guarantee synchronizing them so that the same SPI CLK signal can be used.   Since loading each of the SPI FIFOs take a specific amount of time and each FIFO must be loaded one at a time, this means the SPI HW starts almost immediately when data is available.   Therefore the first SPI Tx will start occur first, the second SPI Tx will start second and the third SPI Tx will start third.   There is a possibly that each SPI data will have a latency added from the delayed start time.   

This is worse when the desired data rate is 20Mbps as the customer is targeting.  In effect,  the maximum FIFO loading latency  for all bytes that can be tolerated is 20ns.    This is impractical on the PSoC even running at 100MHz. If the data rate was much slower, it might not be much of an issue.

Using the common external clocking and using the _Enable() API calls are the only way I see of guaranteeing synchronization.   If the SPI (SCB) or SPI UDB had a HW enable, this would be basically equivalent.

Len
"Engineering is an Art. The Art of Compromise."
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@Len_CONSULTRON  My project is just used to gudie customer how to use DMA+SPI to realize data transmit.  

Back to the original question, below schematic is want i thought about: Control register initial output low,   TX FIFO Level of all three mSPI is set to 1, so the tx_dma terminal remains active once when mSPI is started in fw (mSPI_Start()), but because the AND gate, all three DMA cannot be triggered. Once Control Reg output high, all three DMA will be triggered simultaneously and data will be sent from 3 different array located in SRAM to respective mSPI FIFO. Once data transmission has started, subsequent data will be continuously transferred from array[] to the respective SPI FIFOs until the specified length of data has been transferred.  

If you find this idea problematic or risky, please share your valuable experience!

Vison_Zhang_1-1698078509292.png

 

 

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@Vison_Zhang ,

I recommend only using 1 DMA channel with 3 TDs.  This should be a better approach to guarantee a sequential loading of the R, G and B data words with the lowest latency.

The 3 DMA channels you show above have to separately request the BUS from the CPU. There is a latency to get the BUS and release the BUS.

With only one DMA channel used, there is only one request and the 3 data words loads should operate without interruption.

Len
"Engineering is an Art. The Art of Compromise."
Katherine99
Community Manager
Community Manager
Community Manager
50 replies posted 10 likes received First solution authored

Hi yiru_1705901,

感谢你在英飞凌技术社区的积极提问!对此,我们有一些小小的建议:

由于本界面是英文界面,你在本界面的提问都会统一被送到国外的工程师那边进行回答,但是由于提问内容是中文,所以这些问题又会再次转手给国内的工程师进行回答,这样反而会耽误你获得答案的时间。因此,我们建议你在中文界面中进行提问,这样方便我们的工程师分配对应的FAE 进行回答。

要切换到中文界面,你可以直接点击右上角的语言选择,勾选“CN-简体中文”即可。 

谢谢!

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好的  我没注意这个

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