PSOC6 MCU SPI transfer with DMA

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b3711853
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I am trying to use PSOC6 SPI transfer using DMA channel. I have configured the SPI master to connect with DMA TX and RX channel. The transfer data and length are correct, but the CS pin is not continuously keeping low in the process. Not sure why there are gaps between the byte transfer.

b3711853_0-1618807008351.png

 

 

I have attached my PSOC creator test project for your reference. I am using CY8CKIT-062-WiFi-BT development board to do the test.

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Rakshith
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Hi @b3711853

As we are working from home, I did not have a logic analyzer capable of sampling 25 MHz signals which is why I could not try it out at my end. I was finally able to try out the project with a logic analyzer. Sorry for the delay. 

Changing the channel priority and the Tx FIFO level did help to attenuate the issue but it did not completely resolve the issue. We tried the following things - 

1. In the descriptor settings of DMA_SramToTxfifo, we changed Trigger deactivation and retrigger to Retrigger immediately (pulse trigger)
2. We changed the DMA block of the DMA_SramToTxfifo to DW1. Please refer to this thread for the procedure to do this - Select which DMA block to use . We created a control file with the content - 

 

attribute placement_force of \DMA_SramToTxfifo:DW\ : label is "DMA(0,21)";

 

3. This again did not completely resolve the issue. The digital logic before tr_in was the reason for the delay. We removed the AND gate and the control register.

With these changes, we were able to get a complete transaction where the CS line does not go low - 

spi_dma.PNG

I have attached the complete project and the analyzer file for your reference. Can you please try it out and let me know if this works?

Thanks and Regards,
Rakshith M B

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Rakshith
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Hi @b3711853

I observed that the Deassert SS Between Data Elements option has not been checked in the SPI Master component.
So, the issue could be that the SPI is faster than the DMA. Can you please try increasing the DMA Channel Priority and let me know if that helps? 

Thanks and Regards,
Rakshith M B
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I have set the channel priority of DMA_RxfifoToSram and DMA_SramToTxfifo from 3 to 0. The result is still the same.

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b3711853
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Any update from cypress staff? I have been stuck by this problem for a week...

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Rakshith
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Hi @b3711853

Apologies for the delay in my response.

Can you please try the following things in order?

1)  Change the TX FIFO Level under Trigger Level in the Advanced Tab of the mSPI Configuration Window to 127. Currently, the trigger level is set to 1.

2) If that does not help, can you try reducing the SPI speed? If it works with the reduced SPI speed, it will confirm that the issue is because SPI is running faster than DMA.

Also, can you please share the waveform of the P63 input too?

Thanks and Regards,
Rakshith M B
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b3711853
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1. Set TX FIFO trigger level to 127, result still the same

b3711853_0-1619405196693.png

 

2. Set SPI speed to 14.286MHz, data transfer becomes normal. Using 16.67MHz speed will still see the gaps.

b3711853_1-1619405263941.png

Waveform of the P63 is shown in the red line channel. It is always kept at low level.

 

Using 25MHz SPI speed is very important to my usage. Can you provide a solution to ensure there are no gaps between the data transfer for 25MHz SPI speed? I will not accept manually control the CS pin to ensure low level during the SPI transfer, as the gaps will still degrade the transfer speed to lower than 25MHz.

And also can you try the code on your side instead of every time telling me to try the fix you think of? As it is not efficient and the back and forth is time consuming.

Thanks for the help.

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b3711853
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5 replies posted 5 sign-ins First like received

Any update from cypress staff? It has been a week again...

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Rakshith
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250 likes received 1000 replies posted 750 replies posted

Hi @b3711853

As we are working from home, I did not have a logic analyzer capable of sampling 25 MHz signals which is why I could not try it out at my end. I was finally able to try out the project with a logic analyzer. Sorry for the delay. 

Changing the channel priority and the Tx FIFO level did help to attenuate the issue but it did not completely resolve the issue. We tried the following things - 

1. In the descriptor settings of DMA_SramToTxfifo, we changed Trigger deactivation and retrigger to Retrigger immediately (pulse trigger)
2. We changed the DMA block of the DMA_SramToTxfifo to DW1. Please refer to this thread for the procedure to do this - Select which DMA block to use . We created a control file with the content - 

 

attribute placement_force of \DMA_SramToTxfifo:DW\ : label is "DMA(0,21)";

 

3. This again did not completely resolve the issue. The digital logic before tr_in was the reason for the delay. We removed the AND gate and the control register.

With these changes, we were able to get a complete transaction where the CS line does not go low - 

spi_dma.PNG

I have attached the complete project and the analyzer file for your reference. Can you please try it out and let me know if this works?

Thanks and Regards,
Rakshith M B
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b3711853
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5 replies posted 5 sign-ins First like received

Using the fix can solve the problem now. I think the main reason is using the same DMA block for TX and RX, which cause blocking.