Hi @Azlum
I found the following details from Low Power Application Note and Device Datasheet + Register TRM.
PSoC™ 6 MCU devices allow powering off individual SRAM banks or pages within a bank. The size of pages within a bank depends on the specific device and bank as detailed in the device datasheet. Specific devices will have one or more SRAM banks. Most devices have one bank with a smaller page size (typically 32 KB) for fine-grained control of the amount of SRAM enabled. Any unused page can be disabled by writing to the CPUSs power control registers. This technique is most useful in system deep sleep mode where retaining 64 K SRAM = 7 µA (SIDDS1) and while retaining 256 K SRAM = 9 µA (SIDDS2) as listed in the CY8C61x6 datasheet.
Consult the register TRM of the device for all power control registers.
You can check this register CPUSS_RAM0_PWR_MACRO_CTL0.
As an advanced use case, modification of the project’s linker script can be used with SRAM power down to optimize the total amount of SRAM required or allow custom data placement in support of dynamic SRAM powering.
Thanks, and regards
Sobhit
