Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ 6 Forum Discussions

jmoriarty2569
Level 1
Level 1
First question asked Welcome!

Hello,  I have designed in CY8C6316BZI-BLF53 into a medical product that is going to be used for a clinical trial. I have a handful of boards through our testing have broken and they have done so in the same way. The PSOC is getting power on VDDD and VDDA, but the internal buck isnt working. The latest PCBA that did this had been running a treatment for 40minutes and then it just died in the manner previously described. I couldnt find any schematic on how the power rails are laid out internal to the PSOC and what could have broken exactly in the PSOC for the buck to not work.  On these non working PCBAs I am supplying VDDD and VDDA with 3V from a bench supply. Vbuck measures 2.5V, VDDR_HVL measures 1.5V, VDD_NS measures 3V. All the other rails are 0V. Vind1 and Vind2 are both at 0V. The 32.768kHz crystal is running. Is there any information you can supply to help prevent this from happening or any internal PSOC buck schematic? We are in development and dont want this to become a big issue down the road.

I have noticed that in the literature there is a decoupling cap on Vind2 which is missing in my schematic, but unsure without more information if that is the cause of the issue.


Slainte!
Jeff

0 Likes
1 Solution
ncbs
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 250 replies posted

Hi @jmoriarty2569,

  • vddd - 10uF and 0.1uF through 1kohm inductor at 100MHz
  • vdd_ns - 10uF and 0.1uF through 1kohm inductor at 100MHz (extra cap is present in the schematic)
  • keep the 1uF and 0.1uF caps of VDDIO0 and VDDIO1 separate and do not combine them to make a 4 parallel caps configuration
  • connect 0.1uF cap from Vind2 to ground
  • If BLE is being used, then follow the capacitors (blue in colour) as shown in the figure. Also, each VDDRx pin needs to be separately connected with 1uF and 0.1uF capacitor pair :
    ncbs_0-1632961393948.png

     

Regards,
Nikhil

View solution in original post

0 Likes
1 Reply
ncbs
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 250 replies posted

Hi @jmoriarty2569,

  • vddd - 10uF and 0.1uF through 1kohm inductor at 100MHz
  • vdd_ns - 10uF and 0.1uF through 1kohm inductor at 100MHz (extra cap is present in the schematic)
  • keep the 1uF and 0.1uF caps of VDDIO0 and VDDIO1 separate and do not combine them to make a 4 parallel caps configuration
  • connect 0.1uF cap from Vind2 to ground
  • If BLE is being used, then follow the capacitors (blue in colour) as shown in the figure. Also, each VDDRx pin needs to be separately connected with 1uF and 0.1uF capacitor pair :
    ncbs_0-1632961393948.png

     

Regards,
Nikhil

0 Likes