PSOC 6 free running WDT issue with correct trigger event

[conradc2380]

Hi ,

I am working on the PSOC62 free-running WDT , I followed the example in the following link to use the PDL as i am working on the CM0.

https://github.com/Infineon/Code-Examples-for-the-ModusToolbox-PSoC-6-SDK/blob/mt1.1/CE220060_PSoC6_...

The interrupt part of the sample works fine , but we when I invoke the WDT_RESET_DEMO  the unit does not trigger a reset as per the documentation . In the WDT_RESET_DEMO  mode the code does not use the interrupt ISR to do anything , as i understand it in the background after it has had 2 un handled interrupts  on the 3rd it should do a reset . This does not happen . I have changed the Cy_WDT_SetMatch(0); value between 0 and 32000 to give me 1 second triggers but it also does not change it .

I also would like to reset the WDT counter via my system tick , according to the documentation this cannot be done while the WDT is enabled . So it means every 100ms or so i need to disable the WDT , clear the counter , and re enable it . if the system should go into a freez state in this routine the WDT wont reset either as it is now disabled which is a problem.

Using the Cy_WDT_ClearWatchdog(void) to reset the watchdog seems a bit redundant as it only calls the Cy_WDT_ClearInterrupt(void) function which feel a wasted process time . The question here though is , what does it mean by calling this clear interupt flag that the watchdog resets according to the documentation, does it also reset the counter value?

" The WDT_MATCH bit of the SRSS_INTR register is set
whenever a WDT match interrupt occurs. This interrupt must
be cleared by writing a ‘1’ to the same bit. Clearing the
interrupt resets the watchdog. "

I tried adding this to the systick code to clear  the watchdog every 100ms , it does nothing and in the interrupt mode the watchdog ISR still kicks in.

What is the correct way to clear and reset in software the watchdog to make sure the interrupt or watchdog in reset mode does not fire ?

Attached is the Timer codes C and H files for review , this runs on the PSOC 6 Cy8c6247 cm0 is set to 100Mhz

Any assistance is welcome .

Regards

C

[conradc2380]

Hi ,

Added question here , If the Cy_WDT_ClearWatchdog(void) is called before a interrupt is flah is set in the SRSS int0 register  would it force a interupt or will it still clear the bit  its supposed to ?

Regards

C

[Gautami_12]

Hi @conradc2380 ,

For the code example, CE220060_PSoC6_WatchdogTimer based on ModusToolbox 1.1 to work in (dual core application)CM0+ you need to make a lot of changes in the linker scripts for things to work mainly because 1.1 doesn't have dual-core support. This is where things break for you. And I do not recommend fixing the issues in MTB1.1.

Please use ModusToolbox 3.0 and the above versions for developing any new applications. ModusToolbox 1.1 and 3.0 have completely different project flows and are not directly compatible.

Please download the latest version of ModusToolbox 3.0 and proceed to create your application. The steps are pretty simple and you can find them in the API Reference Manual.

Warm Regards,
Gautami J

[conradc2380]

Hi Gautami,

Thanks for the feedback,

Yes the sample is based on ModusToolbox 1.1, however the basics is still the same for ModusToolbox 3  and the PDL library still supports the same functions as per the previous MTB . Even the Default Cy_watchdog_int() does not work.

Yes i agree the linker script would require the changes , however, I believe the changes were applied successfully making sure the CM0+ is working correctly, I have other peripherals running and interrupting on the CM0 separately from CM4 . I feel comfortable that it is correct. I will share it as well if you are willing to review it 🙂

I don't want to use the Hal on this as this is too much of an overhead and I would like to save as much space and processing speed by using the PDL  even register level in some cases.

Which Api Manula are you refering to , I followed the PDL documentation, but two of my questions are not particularly answered though

"The WDT_MATCH bit of the SRSS_INTR register is set
whenever a WDT match interrupt occurs. This interrupt must
be cleared by writing a ‘1’ to the same bit. Clearing the
interrupt resets the watchdog. "

I tried adding this to the systick code to clear  the watchdog every 100ms , it does nothing and in the interrupt mode the watchdog ISR still kicks in.

What is the correct way to clear and reset in software the watchdog to make sure the interrupt or watchdog in reset mode does not fire ?

[Gautami_12 · Accepted solution]

Hi @conradc2380 ,

“What is the correct way to clear and reset in software the watchdog to make sure the interrupt or watchdog in reset mode does not fire ?”

Please follow the steps mentioned in the 23.3.2 section of PSoC62 Architecture TRM

Also you can use the code snippet in the below screenshot to mask interrupt to prevent further triggers.

Updating Media

To know more about WDT macro’s please look at PSoC6 PDL document .

Also you can refer to the mtb-example-psoc4-wdt for more information .

Warm Regards,
Gautami J