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JaSi_1632926
Level 4
Level 4
Welcome! 25 replies posted 10 replies posted

Hi,

I'm unable to get interrupts to trigger correctly in the M0+ core. The same interrupt works as expected on the M4 core - but it doesn't trigger on the M0+ core.

However, if I debug using MiniProg3 and PsoC Creator, once I add a breakpoint somewhere in the interrupt handler or the main loop, the interrupt is triggered as expected. How does the breakpoints affect interrupts, and how can it make it 'work'?

This is more or less the code:

static int counter = 0;

static void IrqHandler() {

    NVIC_ClearPendingIRQ(IRQ_cfg.intrSrc);

    counter++;

}

__enable_irq();

Cy_SysInt_Init(&IRQ_cfg, &IrqHandler);

NVIC_EnableIRQ(IRQ_cfg.intrSrc);

Reading the counter variable while debugging proves what I've written above - it only increments when I have added a breakpoint.

I don't understand this.

Thanks, Jacob

1 Solution
RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

If you just want to generate an interrupt from M4 to M0, you can use the IPC. Refer to this code example.

http://www.cypress.com/documentation/code-examples/ce223820-psoc-6-mcu-ipc-pipes

View solution in original post

9 Replies
RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

Have you assigned the interrupts to CM0+ in the interrupt tabs in the Design Wide Resources (CYDWR)?

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Yes!

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What's the interrupt trigger source? The interrupt configure IRQ_cfg is defined manually, or by system? If it is defined manually, the configure structure should not be commonly used by two cores.

Fine to attach your project?

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What I'm trying to do is to trigger an interrupt in the M0 core from the M4. To achieve that I have done this in the top design:

pastedImage_0.png

Where the control register is configured as pulse, and the IRQ to trigger on rising edge. That means that the IRQ_cfg (in fact, M4_WAKE_M0_IRQ_cfg) is configured/generated by the system. A write to the control register by the M4 should trigger an interrupt in the M0 core.

Again, if I configure the interrupt in the M4, it seems to trigger as expected.

However, the most intriguing thing is that the interrupts DO occur in the M0 core once I try to debug it - but not without me messing around with breakpoints.

The project is big and not public, unfortunately.

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Just guess - if the interrupt is cleared correctly in ISR? If you not do that, the ISR will be executed just once during free-running.

Under debug mode, you can observe the single ISR triggering.

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I have NVIC_ClearPendingIRQ(M4_WAKE_M0_IRQ_cfg.intrSrc); in the ISR (code snippet updated above), but it doesn't seem to help. Is there anything more that I need to do?

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If changing to something like this:

pastedImage_0.png

It seems to work (counter is one-shot and has period of 1). Is there any more efficient way of accomplish what I want (trigger interrupt on M0 from M4)?

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RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

If you just want to generate an interrupt from M4 to M0, you can use the IPC. Refer to this code example.

http://www.cypress.com/documentation/code-examples/ce223820-psoc-6-mcu-ipc-pipes

Right - I will use that technique instead. Thanks.

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