ModusToolbox 3.0/PSoC 6 Dual CPU Uart problem

[WaHo_350141]

I created two projects for the CY8CPROTO-062-4343W kit.  One was Hello Word and the other empty Dual-CPU.

Hello World worked as expected.  I then changed the code for to use the PDL low level library calls Cy_SCB_UART_Init(),  Cy_SCB_UART_Enable(), and Cy_SCB_UART_PutString(), and the code still worked as expected.  I put the same code in the Dual-CPU.proj_cm4 and the UART doesn't work.  Looking in the memory space, data goes into the FIFO but doesn't get transmitted.  Looking at the memory space the correct SCB clock is selected, and the clock is enabled with the correct parameters.  All generated code in .../config/GeneratedSource for both projects is identical.  After stepping through the code in both projects until UART initialization completes, the UART memory space is identical.  Any ideas as how to resolve this?  I assume it is specific to ModusToolbox 3.0.  My goal is to have the UART code operate in the CM0+ core.

[WaHo_350141 · Accepted solution]

Update -  This is resolved.  I still don't understand it but making the following changes to the CM0+ app caused it to start working:

// Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
Cy_SysLib_Delay(1000);

There was one error in my description of the problem - the UART was processing the data written to the FIFO but the data was not appearing on the output line.  If anyone can explain why the CM0+ change fixed this I would like to understand it.  This is the original CM0+ code:

int main(void)
{
/* Enable global interrupts */
__enable_irq();

cy_rslt_t result;

/* Initialize the device and board peripherals */
result = cybsp_init() ;
if (result != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}

/* Enable CM4. CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */
Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR);

for (;;)
{
Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
}
}