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PSoC™ 6

Mrinal
Level 4
First solution authored 50 replies posted 25 replies posted
Level 4

Hello

What is the maximum input clock frequency for PWM block in PSOC 61x devices?

With system clock at 150MHz, Peri_Clock at 75MHz, I am only able to get 37.5MHz maximum clock input to the PWM block. Is there a way to get faster clock input?

Thank you

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1 Solution
Mrinal
Level 4
First solution authored 50 replies posted 25 replies posted
Level 4

Hello,

Sorry for late response.

Unfortunately, the program still does not work. The compiled project above works perfectly but as soon as I try the same settings in my own program, it does not compile.

Here is the code, and I think I have done exactly the same as the above mentioned design.

Please see if I did something wrong.

Thanks

View solution in original post

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6 Replies
RodolfoGL
Employee
250 sign-ins 5 comments on KBA First comment on KBA
Employee

If you set the system clock to 100 MHz, you can set the PeriClk at 100 MHz as well. (CM4, CM0+ and PeriClk all at 100 MHz), which allows input 50 MHz to the PWM block.

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Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hi @Mrinal 

There is no internal clock in PWM. You must attach a clock source. One of the peripheral clock (PeriClk) dividers should be used as a clock source. 
You can set the FLL or PLL to 100MHz and select it as the source to the peri clock (ensure that the divider value for clk_peri is set to 1) as can be seen in the image below:

Ekta_0-1643010958915.png

Ekta_1-1643011328178.png

You can use the following settings for the clock component to provide a 100MHz input to the PWM:

Ekta_2-1643011652773.png


Best Regards
Ekta

 

 

 

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Mrinal
Level 4
First solution authored 50 replies posted 25 replies posted
Level 4

Thanks for the reply.

Just wondering whether you were able to compile the design with 100MHz input?

Because when I try the same it gives an error saying PWM input clock cannot exceed half of peri clock.

Mrinal_0-1643019938729.png

Please check, perhaps I missed something.

Thanks

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Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hi @Mrinal 

Yes, I was able to compile the project. I also created a sample project for the PSoC 6 WIFI BT Pioneer kit to see if I am able to see the expected output at this frequency and it worked for me.

In the project, I have configured the PWM with an input clock of 100MHz, 32 bit counter, period = 100000000 counts, Compare = 50000000. Therefore the duty cycle of the output PWM is 50% and I observe the LED connected to the PWM output to blink accordingly.

You can compare my clock configurations in the attached project and see if they are similar to yours.

Best Regards
Ekta

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Mrinal
Level 4
First solution authored 50 replies posted 25 replies posted
Level 4

Hello,

Sorry for late response.

Unfortunately, the program still does not work. The compiled project above works perfectly but as soon as I try the same settings in my own program, it does not compile.

Here is the code, and I think I have done exactly the same as the above mentioned design.

Please see if I did something wrong.

Thanks

0 Likes
Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hi @Mrinal 

Sorry for the delay in response I missed your reply

The reason that you observing the issue in your project is that you are using a UDB components in your design. When using UDBs the clock to UDBs cannot exceed half of peri clock.

While in the case of my project I have used a fixed-function PWM block with no UDBs in my design. Therefore I was able to the PWM directly using a peri-clock with a frequency of 100MHz.

Best Regards
Ekta

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