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PSoC™ 6 Forum Discussions

vivekatamantya
Level 1
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5 replies posted 5 questions asked 10 sign-ins

Hello community member,

I have been working with PSoC 6 MCU EVK kit, which is a 062S4 pioneer kit. I am working to get this kit running as the SPI master to send data out to the SPI slave. But things are not quite with the firmware. Here are my details related to the firmware.

SPI master for PSoC 6 -

1. PSoC 6 is set as SPI master (using Modustoolbox to create the project) and using the PDL library to set everything. 
2. SPI master settings: Data rate: 100kbps, 16-bit data width, MSB first, Mode-Motorola (MODE-0), Oversample-16.
3. Data to be sent to SPI slave: 0xF0F0
4. Used PDL library to send the data: Cy_SCB_SPI_Transfer()

The problem is here that, the data is coming early from MOSI as SCLK is coming late when SS is low. Why is it so? The SPI slave expects the data below format:

vivekatamantya_0-1673445538039.png


vs what I am getting.

vivekatamantya_1-1673445580607.png

Yellow-SS, Pink-SCLK, Blue-MOSI

As it can be seen that MOSI is coming before SCLK is driven high, so what is this issue?

Please help me with this.

Thanks,
Vivek Karna

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4 Replies
RodolfoGL
Employee
Employee
250 sign-ins 5 comments on KBA First comment on KBA

This shouldn't affect the integrity of the data, since the SPI slave only samples on the rising edge of the SCLK.

However, I find odd to see such delay between SS de-assertion and the first cycle of SCLK. 

I haven't observed this issue with other PSoC 6 devices. I don't have in hands the 062S4 pioneer kit though.

The only explanation I have is if the SS is controlled in software, rather than in hardware, so such delay would be expected. 

In any case, can you share your project with us? We can try to reproduce this delay in our side.

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vivekatamantya
Level 1
Level 1
5 replies posted 5 questions asked 10 sign-ins

Hello,

How can you say that it will not affect the integrity of the SPI data, the clock pulses are arriving late, so the data coming on MOSI, will only be sampled after the coming of the SPI clock, the data which has come earlier on MOSI has been lost because there was no clock pulse to sample it at the slave end.

However, I can't share the project files due to confidentiality. But, I am sharing with you the snippets of the SPI design file and the code related to the SPI.

vivekatamantya_0-1673599913029.png|

vivekatamantya_1-1673599960420.png

 

vivekatamantya_2-1673599992060.png

Code snippet:

/* Allocate context for SPI operation */
cy_stc_scb_spi_context_t spiContext;

void SPI_ISR(void)
{
Cy_SCB_SPI_Interrupt(SPI1Block_HW, &spiContext);
}

/* Populate configuration structure (code specific for CM4) */
const cy_stc_sysint_t spiIntrConfig =
{
.intrsrc=((IRQn_Type) SPI1Block_IRQ),
.intrPriority = 5U,
};

void SPI_EventHandler(uint32_t events)
{
if(CY_SCB_SPI_TRANSFER_ERR_EVENT == events)
{
printf("\r\nError happenned in SPI.");
}

if(CY_SCB_SPI_TRANSFER_CMPLT_EVENT == events)
{
printf("\r\nEvent is completed.");
}
}

cy_rslt_t rslt;
cyhal_spi_t mSPI;
uint32_t spi_master_frequency = 100000;

void SPIInit(void)
{

//// /* Configuring the SPI master: Specify the SPI interface pins, frame size, SPI Motorola mode and master mode */
//// rslt = cyhal_spi_init(&mSPI, P10_0, P10_1, P10_2, P10_3, NULL, 16, CYHAL_SPI_MODE_00_MSB, false);
////
//// /* Set the data rate to 1 Mbps */
//// rslt = cyhal_spi_set_frequency(&mSPI, spi_master_frequency);
//
/* Configure SPI to operate */
(void) Cy_SCB_SPI_Init(SPI1Block_HW, &SPI1Block_config, /*&spiContext*/NULL);

// /* Hook interrupt service routine and enable interrupt */
// (void) Cy_SysInt_Init(&spiIntrConfig, &SPI_ISR);
//
// NVIC_EnableIRQ(spiIntrConfig.intrSrc);
//
// /* Register callback for event notification.
// * It is better to do this during initialization before SPI is enabled.
// */
// Cy_SCB_SPI_RegisterCallback(SPI1Block_HW, SPI_EventHandler, &spiContext);

/* Enable SPI to operate */
Cy_SCB_SPI_Enable(SPI1Block_HW);

__enable_irq();
}

/*******************************************************************************
* Function Name: main
********************************************************************************
* Summary:
*
* Parameters:
* none
*
* Return:
* int
*
*******************************************************************************/
int main(void)
{
cy_rslt_t result;

/* Initialize the device and board peripherals */
result = cybsp_init();

/* Board init failed. Stop program execution */
if (result != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}

__disable_irq();

/* Initialize retarget-io to use the debug UART port */
result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX,
CY_RETARGET_IO_BAUDRATE);

// /* Board Retarget I/O init failed. */
// if (result != CY_RSLT_SUCCESS)
// {
// RetargetIO = RETARGET_IO_ERR;
// }
//
// /* \x1b[2J\x1b[;H - ANSI ESC sequence for clear screen */
// LOG(LOG_INFO, "\x1b[2J\x1b[;H");
//
// if(Cy_SysPm_Cm0IsDeepSleep())
// {
// LOG(LOG_INFO, "CM0+ is in deep sleep.\n\r");
// }
//
// uint32_t GetResetReason = Cy_SysLib_GetResetReason();
//
// if((CY_SYSLIB_RESET_HWWDT == GetResetReason) || \
// (CY_SYSLIB_RESET_SWWDT0 == GetResetReason) || \
// (CY_SYSLIB_RESET_SWWDT1 == GetResetReason) || \
// (CY_SYSLIB_RESET_SWWDT2 == GetResetReason) || \
// (CY_SYSLIB_RESET_SWWDT3 == GetResetReason))
// {
// LOG(LOG_INFO, "MCU reset due to WDT.\n\r");
// }
//
// /* Enable SysTick */
// Cy_SysTick_Init(CY_SYSTICK_CLOCK_SOURCE_CLK_TIMER, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS);
// Cy_SysTick_Enable();
// Cy_SysTick_DisableInterrupt();
//
// if(true != AppInitialize())
// {
// LOG(LOG_ERR, "Application Initialization failed.\n\r");
// }

SPIInit();

bool here = false;
// Cy_GPIO_Set(HDMI_L_DET_PORT, HDMI_L_DET_NUM);
// Cy_SysLib_Delay(100U);

for (;;)
{
// AppProcessSM();

if(here != true)
{
static uint16_t txBuffer[6] = {0x10FF, 0x11FF, 0x1200, 0x1301, 0x1400, 0x1604};
static uint8_t i = 0U;

if(i < 6U)
{
Cy_SCB_SPI_SetActiveSlaveSelect(SPI1Block_HW, CY_SCB_SPI_SLAVE_SELECT0);

// Cy_GPIO_Clr(HDMI_L_DET_PORT, HDMI_L_DET_NUM);

/* Master: start a transfer. Slave: prepare for a transfer. */
Cy_SCB_SPI_WriteArrayBlocking(SPI1Block_HW, txBuffer, 1);

/* Blocking wait for transfer completion */
while (!Cy_SCB_SPI_IsTxComplete(SPI1Block_HW))
{

}


/* Master: start a transfer. Slave: prepare for a transfer. */
// (void) Cy_SCB_SPI_Transfer(SPI1Block_HW, &txBuffer[i], NULL, 1, &spiContext);
//
i++;
//
// /* Blocking wait for transfer completion */
// while (0UL != (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(SPI1Block_HW, &spiContext)))
// {
//
// }

// Cy_GPIO_Set(HDMI_L_DET_PORT, HDMI_L_DET_NUM);


// Cy_SysLib_DelayUs(1U);
// Cy_GPIO_Set(HDMI_L_DET_PORT, HDMI_L_DET_NUM);

// printf("\r\nStatus: %ld", Cy_SCB_SPI_GetTransferStatus(SPI1Block_HW, &spiContext));
} else {

// while (0UL != (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(SPI1Block_HW, &spiContext)))
// {
// }

here = 1;
printf("\r\nCompleted.");
}

Cy_SysLib_Delay(1000U);
}
}

}


Thank you,
Vivek Karna

 

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vivekatamantya
Level 1
Level 1
5 replies posted 5 questions asked 10 sign-ins

The clock pulse image that I shared with you was for 0xF0F0 data, but in actuality, I have to share an array of data, given in the "txBuffer" array. I was just testing the data integrity with 0xF0F0.

Thanks,
Vivek Karna

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RodolfoGL
Employee
Employee
250 sign-ins 5 comments on KBA First comment on KBA

As I said before, the SPI slave will sample at rising edge of SCLK. If you look at your scope screenshot, you can see that the data sampled by a slave is 0xF0F0, as expected.

You can try to drive 0x70F0. It seems only the first bit is driven earlier on the SPI bus and there is a delay on the SCLK line, but MOSI and SCLK are in sync.

UPDATED:

Here is a screenshot of what I'm seeing on my side:

RodolfoGL_0-1673833341697.png

The only difference between your screenshot and mine is when the SS is asserted and de-asserted. Yours asserts a bit earlier and de-asserts a bit later. An explanation for this would be if the SS is controlled in software. 

You can also observe that is normal for the MOSI to update a few cycles earlier than the SCLK.

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