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antrc_3264986
Level 3
Level 3

I want 3 different structure for nonvolatile memory. Is it possible to have 3 EM_EEPROM in one design.

Also, what start Address should I use for each. A Zero is tested for error.

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1 Solution
ShipingW_81
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

It's possible.

Before get start with the 3 EEPROMs, you need make sure below issues -

- what's the usage of each EEPROM?

- each EEPROM must be accessed by both cores(assuming you use dual-core platform)?

- any other component occupies eeprom space in your project e.g. BLE?

If you drap 3 EEPROM components on your project topdesign, the system would automatically allocate both cores with same eeprom flash space(in segment  .cy_em_eeprom) for each component. The start address for each EEPROM component will fixed sequentially based on the data array length defined for each component in Em_EEPROM(_x).c. Please find the start address in respective .map file or below code snippet for each core.

.cy_em_eeprom  0x14000000      0xc00

*(.cy_em_eeprom)

.cy_em_eeprom  0x14000000      0x800 .\CortexM0p\ARM_GCC_541\Debug\Em_EEPROM.o

                0x14000000                Em_EEPROM_em_EepromStorage

.cy_em_eeprom  0x14000800      0x200 .\CortexM0p\ARM_GCC_541\Debug\Em_EEPROM_1.o

                0x14000800                Em_EEPROM_1_em_EepromStorage

.cy_em_eeprom  0x14000a00      0x200 .\CortexM0p\ARM_GCC_541\Debug\Em_EEPROM_2.o

                0x14000a00                Em_EEPROM_2_em_EepromStorage

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4 Replies
ShipingW_81
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

It's possible.

Before get start with the 3 EEPROMs, you need make sure below issues -

- what's the usage of each EEPROM?

- each EEPROM must be accessed by both cores(assuming you use dual-core platform)?

- any other component occupies eeprom space in your project e.g. BLE?

If you drap 3 EEPROM components on your project topdesign, the system would automatically allocate both cores with same eeprom flash space(in segment  .cy_em_eeprom) for each component. The start address for each EEPROM component will fixed sequentially based on the data array length defined for each component in Em_EEPROM(_x).c. Please find the start address in respective .map file or below code snippet for each core.

.cy_em_eeprom  0x14000000      0xc00

*(.cy_em_eeprom)

.cy_em_eeprom  0x14000000      0x800 .\CortexM0p\ARM_GCC_541\Debug\Em_EEPROM.o

                0x14000000                Em_EEPROM_em_EepromStorage

.cy_em_eeprom  0x14000800      0x200 .\CortexM0p\ARM_GCC_541\Debug\Em_EEPROM_1.o

                0x14000800                Em_EEPROM_1_em_EepromStorage

.cy_em_eeprom  0x14000a00      0x200 .\CortexM0p\ARM_GCC_541\Debug\Em_EEPROM_2.o

                0x14000a00                Em_EEPROM_2_em_EepromStorage

Thank you for the answer. I am still having issues.

I have an Init for the EM_EEPROM in my main. I cannot set the StartAddress (see code below) because of const declarations in 6 places in the PDL library. Editing the generated code only last until I generate again.

// Set Start Address to work in flash     

Em_EEPROM_TubeSensor_config.userFlashStartAddr =

    (uint32_t)Em_EEPROM_TubeSensor_em_EepromStorage;

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Do you mean you want to assign a eeprom memory space with a absolute start address?

Possible to attach a simple project to show us the issue you are facing?

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MeenakshiR_71
Employee
Employee
100 likes received 50 likes received 25 likes received

Yes, you can have any number of emulated EEPROM area in your code as long as you have space available in your flash. You can simply place as many Em_EEPROM components in the TopDesign as you wish and select the region to use for each Em_EEPROM However, certain things to consider -

  1. It is recommended to use the Emulated EEPROM region (0x14000000 to 0x14007FFF: 32 KB) for this purpose.
  2. You can use User flash as well for the purpose. However, when doing so keep in mind the Read-While-Write (RWW) limitation explained in section 12.5.4 (Write Row System call) of the PSoC 6 Architecture TRM. The tricky part here is figuring out the portion of code that is being executed (in both cores), from which Flash region it is getting executed, whether it is running from cache and in which emulated EEPROM region you are going to write. The simplest way to overcome this limitation would be to enable Blocking flash write in the Em_EEPROM component - which will make sure both cores do not execute any code from flash during the write process.
  3. The RWW limitation explained in point 2 also applies to the EEPROM region i.e. you cannot update two emulated EEPROM section in the code simultaneously.

Let me know if you need any further clarification with regards to EEPROM usage.

Regards,

Meenakshi Sundaram R

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