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PSoC™ 6 Forum Discussions

vinu_gk
Level 2
First solution authored 10 replies posted 5 questions asked
Level 2

Hi,

I need two GPIO interrupts on PORT0. The pins chosen were 0.4 and 0.2. However, pin 0.2 didn't trigger any interrupt.

Then i found some links (of PSOC4) saying that external interrupts of the same port should be adjacent / contiguous. 

Later, when i changed the pins to 0.3 and 0.4 it worked. So -

  1. Should the GPIO interrupt pins of same port be adjacent ?
  2. If yes, why  does PSOC have such a constrain for interrupt pins ?
  3. Is there any document referring to the same ?

regards,

VG

@shibin 

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1 Solution
AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @vinu_gk ,

I did some test for Port 9 and did not find the same issue present there but only for Port 0.

I used individual pins instead of using a component to hold both Pin 0.2 and Pin 0.4 and that fixed the issue.

I have attached the project here for your reference.

Warm Regards
Alen

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9 Replies
AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @vinu_gk ,

Can you please let me know if you are using a custom board or a PSoC Evaluation board?

If it is a PSoC Evaluation board, can you let me know of the name of the same?

Warm Regards
Alen

vinu_gk
Level 2
First solution authored 10 replies posted 5 questions asked
Level 2

Hi @AlenAn14 ,

I am using PSOC6 WiFi BT Pioneer Kit  ( CY8CKIT-062-WiFi-BT ) evaluation board.

regards,

VG

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AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @vinu_gk ,

  1. Should the GPIO interrupt pins of same port be adjacent ?
    A. No they need not be. Each port has only one NVIC line ( i.e. its not that each pin has an NVIC line as these are limited when compared to the number of GPIO pins on the MCU (this is because if there are 12 ports, then 12*8 = 96 NVIC lines for the pins which leaves little NVIC lines for remaining timers, I2C, USB . etc peripherals). Hence for 12 ports there are only 12 NVIC lines so other peripherals can have sufficient NVIC lines as well.)
    Since there is only one NVIC line for the port, but we have 8 pins, to determine which pin triggered the interrupt, we have to use the API Cy_GPIO_GetInterruptStatus() inside the ISR of the port of the pin that triggered the interrupt (rising/falling/both edges).
    A sample snippet of the ISR handler is as follow:

    void port0_ISR()
    {
    	printf("\r\n[ INTERRUPT ] : Port 0\r\n");
    
        	if(Cy_GPIO_GetInterruptStatus(P0_2_PORT, PIN_2_NUM) )
        	{
        		printf("[ INTERRUPT ] : Pin 0 2 Detected\r\n");
        		Cy_GPIO_ClearInterrupt(P0_2_PORT, PIN_2_NUM);
        	}
        	if(Cy_GPIO_GetInterruptStatus(P0_3_PORT, PIN_3_NUM))
        	{
        		printf("[ INTERRUPT ] : Pin 0 3 Detected\r\n");
        		Cy_GPIO_ClearInterrupt(P0_3_PORT, PIN_3_NUM);
        	}
        	if(Cy_GPIO_GetInterruptStatus(P0_4_PORT, PIN_4_NUM) )
        	{
        		printf("[ INTERRUPT ] : Pin 0 4 Detected\r\n");
        		Cy_GPIO_ClearInterrupt(P0_4_PORT, PIN_4_NUM);
        	}
    }​



  2. Is there any document referring to the same ?
    A. In the PSoC 62 architecture TRM, page 249, you get a detailed overview of the GPIO NVIC architecture and how the same can be used for handling interrupts from individual pins of a port.

Hope this helps

Warm Regards
Alen

vinu_gk
Level 2
First solution authored 10 replies posted 5 questions asked
Level 2

 Thanks @AlenAn14 . But for some reason, my interrupt test code of evk didnt work with adjacent pins.

 

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AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @vinu_gk ,

Can you share the firmware/project where you tested this interrupt issue on?

Like a stripped down version of the code that demonstrates the issue you have mentioned.

Warm Regards
Alen

vinu_gk
Level 2
First solution authored 10 replies posted 5 questions asked
Level 2

I have attached the example project in which i was testing the same. I am getting interrupt for SW2 (P0.4), but no interrupt for P0.2 ( header J4, D7 ).

Please have a look.

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AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @vinu_gk ,

I did some test for Port 9 and did not find the same issue present there but only for Port 0.

I used individual pins instead of using a component to hold both Pin 0.2 and Pin 0.4 and that fixed the issue.

I have attached the project here for your reference.

Warm Regards
Alen

vinu_gk
Level 2
First solution authored 10 replies posted 5 questions asked
Level 2

Hi @AlenAn14 

Thanks. I have also confirmed the same here.

So the PDL GPIO pin component has some issue with multiple input pin assignment for Port 0 interrupt.

regards,

Vinu

 

 

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AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @vinu_gk ,

Yes, this seems to be the case.

I will create a ticket with the internal team regarding this issue.

Thank you for pointing this issue out.

Warm Regards
Alen