Identification of the Power - On - Reset, Brown out Reset, External Reset or Backup Reset

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Umer_Idrees
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Hi,

I need to differentiate between (Power-on Reset, Brownout Reset, External reset, and Backup Reset). Going through the Technical Architecture Reference Manual shows if no bit of the Reset Cause register is set, then it could be due to Power_on reset, Brownout Reset, or External reset. But differentiate between these four is required (Power-On Reset, Brownout Reset, Backup Reset, and External reset).

Any help regarding this would be helpful. Thanks.

Regards,

Umer Idrees

 

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The problem is that under some weak battery conditions, the processor doesn't always get to run long enough to process the interrupt . This results in an endless reboot loop. So detecting that BOD has already occurred, we can trap in this state and hold under either conditions improve, or the battery totally gives out.

 

We have done our own implementation of the BODKEY featre from Psoc4 using one of the psoc6 backup domain registers to detect corruption (and therefore a BOD event).

 

 

 

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RodolfoGL
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250 solutions authored 250 sign-ins 5 comments on KBA

I don't know any method to differentiate all of them.

However, for the brownout reset, you might be able to detect this event before it happens by using the Low-Voltage Detect driver. Refer to:

https://infineon.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__lvd.html

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Umer_Idrees
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RodolfoGL, 

Thanks, but we need to identify the cause of each reset (Power-On - Reset, External Rest, or Backup Reset).  Any help regarding this would be greatly appreciated. Thanks.

 

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Hello,

Power-on Reset condition occurs during device power-up. POR holds the device under reset until the VDDD reaches the threshold voltage as specified in the device datasheet.

Brownout reset monitors the chip digital voltage supply VDDD and generates a reset if VDDD falls below the minimum logic operating voltage specified in the device datasheet

External reset (XRES) is a reset triggered by an external signal that causes immediate system reset when asserted. The XRES pin is active low – a logic ‘1’ on the pin has no effect and a logic ‘0’ causes reset. The pin is pulled to logic ‘1’ inside the device. XRES is available as a dedicated pin.

Please refer to the section 21. Reset System in the Architecture datasheet for more information.

Thanks,
P Yugandhar.

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I was looking for the same functionality. The interrupt can help you on the way down, can't help you on the way up.

There are cases when you want to know if(and after) a BOD has occurred.  A common is case is when external power may be weak, and the system may only come up briefly before resetting, and which can result in a continuous reset loop.  PSOC4 had a BODKEY method that could be used to detect (corruption of the BODKEY register value) in this case.

I was looking for the same thing in PSOC6, but doesn't seem to have this function.

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Yugandhar
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500 solutions authored 1000 replies posted 5 likes given

Hello @John_K , 


However, for the brownout reset, you might be able to detect this event before it happens by using the Low-Voltage Detect driver. Refer to:

https://infineon.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__lvd.html


you can use the Low-Voltage Detect driver for BOD reset. The LVD block provides a status of currently observed VDDD voltage and triggers an interrupt when the observed voltage crosses an adjusted threshold.

Thanks,

P Yugandhar. 

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The problem is that under some weak battery conditions, the processor doesn't always get to run long enough to process the interrupt . This results in an endless reboot loop. So detecting that BOD has already occurred, we can trap in this state and hold under either conditions improve, or the battery totally gives out.

 

We have done our own implementation of the BODKEY featre from Psoc4 using one of the psoc6 backup domain registers to detect corruption (and therefore a BOD event).