How to set PSOC6 ADC Sampling Frequency to 2KHz?

[Akash-USC]

Hi All,

Could any of you help me in setting the sampling frequency of the PSOC6 chipset ADC to 2KHz?

The minimum clock frequency the ADC can take in is 1.7MHz and I am unable to find a reasonable way to lower the sampling frequency.

Any suggestions are welcome. Thanks in advance.

[Arpit_S]

Hi

Can you please share which Development Environment are you using? ModusToolbox or PSoC Creator?

Regards
Arpit Srivastav

[Len_CONSULTRON · Accepted solution]

Akash,

There is a reason that the AD input clock needs to be that high.   It is usually due to the ability of the input cap of the ADC to retain a charge.  This capacitance tends to be very small (<10pF).  Since the cap is a silicon cap it tends to be 'leaky'.  Taking too long for the ADC conversion to complete (eg. 500us) could see much of the voltage across it dissipate.

I believe what you want is not a 2KHz sampling rate but a 2KHz conversion rate.

There is a SOC (Start of Conversion) input that you can source a 2KHz clock to.  This will force each conversion at a 2KHz rate while the ADC clock resolves the ADC count at the faster rate.

You can then use the EOC (End of Conversion) output to trigger an isr to process the completed conversion or you can use the IsConversionComplete() function to determine when it is done.

I believe this is your best solution.