Hi,
Although Sending and Receiving Serial data by firmware need a couple of MCUs, this topic is in PSoC 6 Forum!
And a PSoC 6 often has a couple of cores, Cortex-M0+ and Cortex-M4.
So I tried let Cortex-M4 send bytes, and let Cortex-M0+ to receive them.
It's great that we can test with only a single board 😉
I used CY8CKIT-062-WIFI-BT
The schematic was (connect P0[2] and P5[6] to let cores communicate)
Cortex-M0+ main.c
=================
#include "project.h"
#include "stdio.h"
#define BIT_DELAY 10
#define SW_LOW (0u)
#define SW_HIGH (1u)
#define delay(a) CyDelayUs(a)
char str[128] ; /* print buffer */
void print(char *str)
{
UART_PutString(str) ;
}
void init_hardware(void)
{
__enable_irq(); /* Enable global interrupts. */
UART_Start() ;
/* Enable CM4. CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */
Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR);
}
void splash(void)
{
sprintf(str, "Software Serial Test (%s %s)\n", __DATE__, __TIME__) ;
print(str) ;
}
uint8_t sw_recv_byte(void)
{
int bit_count = 8 ;
uint8_t data = 0 ;
while(Cy_GPIO_Read(SW_RX_0_PORT, SW_RX_0_NUM) == SW_HIGH) {
delay(BIT_DELAY/2) ;
}
delay(BIT_DELAY) ;
while(bit_count--) {
data <<= 1 ;
if (Cy_GPIO_Read(SW_RX_0_PORT, SW_RX_0_NUM) == SW_HIGH) {
data |= 0x01 ;
}
delay(BIT_DELAY) ;
}
if (Cy_GPIO_Read(SW_RX_0_PORT, SW_RX_0_NUM) != SW_HIGH) {
print("SW_RX, Stop bit missing!\n") ;
}
return( data ) ;
}
int main(void)
{
uint8_t data = 0 ;
init_hardware() ;
splash() ;
for(;;)
{
data = sw_recv_byte() ; /* this function blocks */
sprintf(str, "\tCM0 received 0x%02X\n", data) ;
print(str) ;
}
}
=================
Cortex-M4 main.c
=================
#include "project.h"
#include "stdio.h"
char str[128] ; /* print buffer */
void print(char *str)
{
UART_PutString(str) ;
}
#define BIT_DELAY 10
#define SW_LOW (0u)
#define SW_HIGH (1u)
#define delay(a) CyDelayUs(a)
void sw_send_byte(uint8_t byte_to_send)
{
uint8_t mask = 0x80 ;
Cy_GPIO_Write(SW_TX_0_PORT, SW_TX_0_NUM, SW_LOW) ; /* start bit wannabe */
delay(BIT_DELAY) ;
while(mask) { /* sending 8 bits MSB first */
if (byte_to_send & mask) {
Cy_GPIO_Write(SW_TX_0_PORT, SW_TX_0_NUM, SW_HIGH) ;
} else {
Cy_GPIO_Write(SW_TX_0_PORT, SW_TX_0_NUM, SW_LOW) ;
}
mask >>= 1 ;
delay(BIT_DELAY) ;
}
Cy_GPIO_Write(SW_TX_0_PORT, SW_TX_0_NUM, SW_HIGH) ;
delay(BIT_DELAY) ; /* stop bit wannabe */
}
int main(void)
{
uint8_t byte_to_send = 0x00 ;
__enable_irq(); /* Enable global interrupts. */
Cy_GPIO_Write(SW_TX_0_PORT, SW_TX_0_NUM, SW_HIGH) ;
CyDelay(1000) ; /* wait for Cortex-M0 to be ready, may be too much */
for(;;)
{
sprintf(str, "CM4 sending 0x%02X\n", byte_to_send) ;
print(str) ;
sw_send_byte(byte_to_send) ;
byte_to_send = (byte_to_send + 1) % 0x100 ;
CyDelay(1000) ;
}
}
=================
The debug output via Tera Term was
As far as I tried, 2us for 1 bit did not work, but so far 10us for 1 bit seems to be working.
As usual, your mileage may vary
moto
P.S. Alas, this was the first program I intentionally used both cores of PSoC 6 orz
