Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ 6

ChRe_4711096
Level 4
50 replies posted 25 replies posted 25 sign-ins
Level 4

In the attached project I'm getting warnings about asynchronous clock paths and setup time violations.

In general:

  • how do I interpret the warnings, based on the timing report?
  • are there any standard recipes to fix the underlying problems?

And specifically: how do I fix the timing issues in the attached project?

0 Likes
1 Solution
Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hello ChRe_4711096

Please refer to the appnote on Digital design best practices which mentions in detail about setup time violation, STA reports and setup time violation. Link to the appnote: https://www.cypress.com/documentation/application-notes/an81623-psoc-3-psoc-4-and-psoc-5lp-digital-d...

Though the appnote is for psoc 3, 4 and 5lp. The concepts in the appnote will apply to PSoC 6 as well.

The asynchronous path error generally differences between the clocking network and the DSI. You should add Sync Components to block outputs that are routed to inputs of UDB-based Components.

Best Regards

Ekta

View solution in original post

4 Replies
Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hello ChRe_4711096

Please refer to the appnote on Digital design best practices which mentions in detail about setup time violation, STA reports and setup time violation. Link to the appnote: https://www.cypress.com/documentation/application-notes/an81623-psoc-3-psoc-4-and-psoc-5lp-digital-d...

Though the appnote is for psoc 3, 4 and 5lp. The concepts in the appnote will apply to PSoC 6 as well.

The asynchronous path error generally differences between the clocking network and the DSI. You should add Sync Components to block outputs that are routed to inputs of UDB-based Components.

Best Regards

Ekta

ChRe_4711096
Level 4
50 replies posted 25 replies posted 25 sign-ins
Level 4

The best practices appnote is certainly helpful, but to be honest it seems that correct placement of sync blocks is a bit of a guessing game especially in systems with closed loops that involve async components.

0 Likes
PSa_795526
Level 4
10 replies posted 5 solutions authored 5 replies posted
Level 4

Hi,

In the project, the component "Adc_Filter_UDB_1" does not seem to be able to operate at a high frequency of 72 MHz due to some internal delays in the component. A screenshot of the project's STA report below shows this:

STA report screenshot.jpg

I tried reducing its clock "clk_udb" by half using a divider of 2 on Clk_Peri. After this, the project builds without STA warnings, as attached. Would this be acceptable for your application ?

Best Regards,

Prem Sai

ChRe_4711096
Level 4
50 replies posted 25 replies posted 25 sign-ins
Level 4

It would probably be acceptable to reduce clock speed for this component.

Let's add more context: the Adc_Filter_UDB contains a 16-bit datapath that receives ADC samples and then evaluates them based on sign and value - like a comparator with configurable deadband. It's surrounded by a 4:1 mux/demux and of course the ADC and in the actual target application serves 4 other moderately complex components (BLDC ESCs). If I'm interpreting the timing report correctly, the setup time _within_ the 16-bit datapath is too long, indicating routing congestion within that component. That's somewhat in line with the target design barely fitting into the available routing.

0 Likes
Top labels