Greg,
Good question. I don't think that Infineon (Cypress) ever published data about the specific current consumption of the TRNG.
Here's a TRNG overview block diagram:
In general principle, a true MOS digital circuit that is static (no change in logic state) should consume << 1uA.
It's only during the switching of the logic state does the circuit(s) consume power. This would account for >99% of average current used when active.
In my study, I could not easily find a register to cut power to these circuits. There probably is one. It is probably used to cut power when the IC is in lower-power modes. Chances are that the control to cut power is probably the same one to cut power to the whole crypto section of the IC.
If using a low-power mode is not doable for your application then you need to try to "disable" the following signals:
- RO11_EN
- RO15_EN
- GARO15_EN
- GARO31_EN
- FIRO15_EN
- FIRO31_EN
- SAMPLE_CLOCK_DIV[] (if possible)
I haven't peeked into the cyhal_trng_free() function code to see if it disables any of the enables mentioned. If it does, job done (?).
If not, you would need to potentially do it yourself by turning off the bits in the CRYPTO_TR_CTL1 register.
The SAMPLE_CLOCK_DIV is controlled in the CRYPTO_TR_CTL0 register and it doesn't appear that you can turn it off. However, you can reduce the output frequency by /255. That might help.
I suspect the reason that Cypress never specified the TRNG current used is that it is probably < 20uA. For them to characterize that would require the TRNG be running in low-power mode which the power is probably removed in the LP mode. Characterizing the current in active mode is probably like measuring a small stream of water in a river. Not easy and highly subject to large fluctuations.
Greg,
Good question. I don't think that Infineon (Cypress) ever published data about the specific current consumption of the TRNG.
Here's a TRNG overview block diagram:
In general principle, a true MOS digital circuit that is static (no change in logic state) should consume << 1uA.
It's only during the switching of the logic state does the circuit(s) consume power. This would account for >99% of average current used when active.
In my study, I could not easily find a register to cut power to these circuits. There probably is one. It is probably used to cut power when the IC is in lower-power modes. Chances are that the control to cut power is probably the same one to cut power to the whole crypto section of the IC.
If using a low-power mode is not doable for your application then you need to try to "disable" the following signals:
- RO11_EN
- RO15_EN
- GARO15_EN
- GARO31_EN
- FIRO15_EN
- FIRO31_EN
- SAMPLE_CLOCK_DIV[] (if possible)
I haven't peeked into the cyhal_trng_free() function code to see if it disables any of the enables mentioned. If it does, job done (?).
If not, you would need to potentially do it yourself by turning off the bits in the CRYPTO_TR_CTL1 register.
The SAMPLE_CLOCK_DIV is controlled in the CRYPTO_TR_CTL0 register and it doesn't appear that you can turn it off. However, you can reduce the output frequency by /255. That might help.
I suspect the reason that Cypress never specified the TRNG current used is that it is probably < 20uA. For them to characterize that would require the TRNG be running in low-power mode which the power is probably removed in the LP mode. Characterizing the current in active mode is probably like measuring a small stream of water in a river. Not easy and highly subject to large fluctuations.
