How is I2C_1_CLK_FREQ_HZ initialized in Generated Source?

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
JoYa_4324706
Level 3
Level 3
5 sign-ins First solution authored 10 replies posted

Hi,

I'm trying to use 400kbps as desired data rate for my I2C component, but only to discover that the SCB clock (kHz) generated by PSoC Creator itself is set to 7500, which apparently to be out of range. Is there anyway to help understand how this clock value is generated while I'm not using external clock terminal?

Thanks!

Best,

Joseph

0 Likes
1 Solution
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

I think that the clock to the SCB block is not directly to the I2C clock but for the oversampling it is supposed to be 16x faster.

While ago, I posted the following test program,

MCU Tester, a Swiss Army Knife for PSoC (CY8CKIT-062-BLE version)

Although I2C speed is set to 100 (kbps) you can easily changed it to 400 (kbps) from the schematic > I2C tab

001-I2C-400K.JPG

Then could you test if the program works with your 400kbps component(s)?

moto

View solution in original post

0 Likes
1 Reply
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

I think that the clock to the SCB block is not directly to the I2C clock but for the oversampling it is supposed to be 16x faster.

While ago, I posted the following test program,

MCU Tester, a Swiss Army Knife for PSoC (CY8CKIT-062-BLE version)

Although I2C speed is set to 100 (kbps) you can easily changed it to 400 (kbps) from the schematic > I2C tab

001-I2C-400K.JPG

Then could you test if the program works with your 400kbps component(s)?

moto

0 Likes