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PSoC™ 6 Forum Discussions

SvMe_4718011
Level 1
Level 1
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Hello,

How can I get the maximum Datarate from the UDB to RAM?

I use 32Bit wide Readacces to the FIFOs. It looks like I need round about 10 Clock Cycles for a read access of a single 32bit Word. Indipendent if I use the M0 CPU or the DMA.

I the post  PSoC6 Memory and DMA Performance there was mentioned that the Taa time is 2 but depends on the device. I use a CYBLE-416045-02. Is there a PSOC6 with better acces Times regarding the UDB? How should I configure the UDB for maximum Perfomance from FIFO to RAM and what is the maximum possible Speed there?

Regards

Sven

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1 Solution

Sven,

As Rodolfo is pointing out, using the DMA has some minor latencies and some clock cycles for pre-DMA setup and post-DMA cycle for completion.  Maybe someone can find a KBA about these factors.

If you have a larger FIFO available, you can dump multiple long words at a time minimizing the pre- and post- effects.

Len

PS:  Are you willing to share your project with the forum?  At least a stripped down version so we can reproduce your results can possibly suggest a 'better' solution?

Len
"Engineering is an Art. The Art of Compromise."

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Len_CONSULTRON
Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

Sven,

Can you be more specific about which UDB elements (components) you are using?  In general, each UDB block can be clocked at 80MHz.  Depending how that UDB block is hooked up to other blocks to implement that component function will lower the operational data rate.

If you have already constructed the UDB logic for your design, there should be a timing report that might yield effective data rates.

Len

Len
"Engineering is an Art. The Art of Compromise."
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To get the fastest read rate from a UDB FIFO, you need to do the two following things:

- Configure the datapath to be clocked by the bus clock. In the Datapath Configurator tool, there is a config register called "FIFO FAST". It has two options, "DP" or "BUS". Choose "BUS".

- The MIMO bus is clocked by the Slow Clock. Configure the Slow Clock to be the fastest, which is 100 MHz.

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Hi,

I have used that settings allready and in get a reat of 11MHz reading with a DMA from the "xxx__32BIT_F0_REG". That is equvalent to 9 Clock Cycles at 100MHz

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I guess you are controlling the DMA using the FIFO level from the UDB, doing single transfers per trigger.

If you want to transfer faster than that, you might be able to configure more than a single transfer if your UDB logic can keep up feeding the FIFO at a faster rate.

For example, configure the DMA to transfer 256 words on one trigger.

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Sven,

As Rodolfo is pointing out, using the DMA has some minor latencies and some clock cycles for pre-DMA setup and post-DMA cycle for completion.  Maybe someone can find a KBA about these factors.

If you have a larger FIFO available, you can dump multiple long words at a time minimizing the pre- and post- effects.

Len

PS:  Are you willing to share your project with the forum?  At least a stripped down version so we can reproduce your results can possibly suggest a 'better' solution?

Len
"Engineering is an Art. The Art of Compromise."
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Hi Len,

I use a Continues DMA Transfer with only one Initial Trigger to get that data rate. To get that working I trimmed my sample rate in regards to the CLK_Peri so that I do not get an FIFO over and underrun.

I will try to create a striped down version I can post here.

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