- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I have a pin set to high impedance digital and an external pull up resistor of 10k ohm to 3.3V. For some reason the pin stays at 2.35V instead of going to 3.3V.
It almost seems like the pin has some internal pull down that I am fighting.
I am using chip CY8C6347LQI-BLD52, pin P7.2
Any ideas why it isn’t going to 3.3V?
- Labels:
-
PSoC 6 MCU
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
RyWi,
Can you share your project with on thread?
"Engineering is an Art. The Art of Compromise."
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
RyWi,
Thanks. Downloaded your project. No issue with 'BUT' (P7.2)
Are you using a Cypress Kit or eval board? OR any eval board? If so, it might be possible that the eval board may have a ~25K resistance to GND externally.
"Engineering is an Art. The Art of Compromise."
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
This is a custom PCB. It had a pull up resistor to 3.3V, but I removed it.
I checked two other pins I have access to P6.0, and P6.1 and those work correctly.
The problem also shows itself if I do resistive pull up/down by the high only being 2.35V instead of 3.3V. Low is correct at 0V.
Looking at the PCB schematic there is definitely not an external pull down resistor.
Is it possible some setting for internal pull up is enabled in the code somewhere?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
RyWi,
I tried your project on my Cy8CKIT-062-BLE eval board which uses the same CPU.
I don't have access to P7.2 so I moved it to P7.3. When I build your project and place a pull-up bias resistor on P7.3 I get 3.3V. I don't know what to say.
Since you're using a custom PCB, with the power off, perform a resistance measurement from P7.2 to GND. If you're seeing about 25K, you have to question if there is a trace short to another circuit or damaged PSoC6.
"Engineering is an Art. The Art of Compromise."
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
After a lot of digging we found out that the the pin behaves correctly if we change the VDDA voltage from 1.8V to 3.3V.
Right now we have:
VDDD- 3.3V
VBACKUP - 3.3V
VDDIO1 - 3.3V
VDDA, VDDIO_A - 1.8V
VDDIO_0 - 1.8V
If we change VDDA and VDDIO_0 to be at 3.3V then the high impedance mode works correctly. We can't do this for normal operation however.
Any ideas what could be going on here? And if there is any risk to damaging the psoc if we keep the voltage levels where they are?
Also for reference the misbehaving pin, P7.2, is on VDDIO1 which is always at 3.3V
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
RyWi,
In a different PSoC (PSoC5 I believe) VDDA must be > or = to VDDD. I've been looking for this requirement in the TRMs and the datasheet for the PSoC6 but could not find it.
Still looking...
"Engineering is an Art. The Art of Compromise."
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
RyWi,
Have you received an acceptable answer to issue?
I couldn't find any prerequisites on the PSoC6 for VDDA to be >= to VDDD. This is a requirement for the PSoC5LP CPU.
However, your evidence appears to confirm this as well.
Is there a reason that you need 1.8V on VDDA?
It might be possible to achieve your specific requirements with VDDA = 3.3V.
If you can share your project requirements regarding the analog subsystem, we may be able to counsel you as to solutions.
"Engineering is an Art. The Art of Compromise."