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PaSw_2578827
Level 4
Level 4
25 replies posted 10 replies posted 10 questions asked

Hi folks,

I'm trying to achieve a half-duplex UART on a single bidirectional pin ideally with an SCB UART component. Basically my question and schematic is identical to this one: https://community.infineon.com/t5/PSoC-6/UART-2-5-and-PSoC-6/m-p/76120#M1963

Unfortunately I can't post on that thread as it is marked as resolved but to the best of my knowledge that's not actually a solution to the primary issue of routing the RX/TX signal. The issue I'm having is that the SCB has fixed pins for RX and TX and the the fitter is unable to route them to a single pin.

I can do this with UDB, unfortunately Cypress no longer supports UDB UART on PSOC6 (which is crazy to me), I was able to find a third party component that works but I'm out of resources. I cannot make any changes to the external hardware and the actual RX pin is unavailable anyway.

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PaSw,

... My RX and TX terminals are connected to a bufoe component controlled by the TX_EN, this all works fine for the UDB UART, but the issue is that the UART SCB has fixed RX and TX connections and it won't allow me to route to a single bidirectional pin.  


You are correct.   On the PSoC6s (and later PSoC4s) Cypress elected to reduce the GPIO functionality of the Digital Routing 'Fabric'.  options.   From my research, I cannot find a way for a GPIO to be assigned to be Bidirectional or as a Input and Output pin with Output enable.

Unless someone can show how a GPIO pin can be configured as listed above, you have to assign a separate pin for Input and for an Output as open drain and physically connect the pins together outside the IC.

The TopDesign allows for a "BiDirectional" and a Input/Output with OE, but I have yet to get either of these GPIO configurations to route and build.   It these GPIO types are not allowed, Infineon should remove them from the component catalog for the PSoC6.

I have two solutions that do route.

Solution #1

Len_CONSULTRON_0-1646835834627.png

This solution has the advantage of eliminating the Tx_oe control from the UART.   However, it basically requires a pullup on the GPIO.  I configured the Rx input as an digital input with Pullup.  This eliminated an external pullup resistor.    

The potential downside is the data rate.  Since the Tx output is open drain, it pulls low strongly but an inactive high is a float.  The the float high is dependent on the value of the pullup resistor.   A lower value a faster float high.

Solution #2

Len_CONSULTRON_1-1646836185676.png

This solution theoretically could have faster data rates since the external transceiver IC can switch the driver off and the receiver on faster.

The downside is that it requires the Tx_oe signal through a GPIO to control the transceiver direction.

As I mentioned earlier I have an identical setup to the first post in the thread I originally linked, and the same problem they had.  According  to that thread their problem was resolved but the actual resolution is not provided. I posted this to try and clarify what their resolution is as it is apparently possible (or else that thread is mislabeled as resolved).

It was my "solution" that was apparently selected as "solved" on the thread you posted.   However,  sometimes solutions are accepted by the forum moderator and not the original person posting.   Therefore it is not clear which idea in the discussion that was adopted and working.

The solutions I list above do build/route.   Due to the internal architecture of the PSoC6, it is much more limited than what is available on the PSoC5.

 

Len
"Engineering is an Art. The Art of Compromise."

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

PaSw,

Which PSoC6 device are you trying to target?

Len
"Engineering is an Art. The Art of Compromise."
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The exact part is the CY8C6247BZI-D54, this is a retrofit to existing hardware I only have scope to change firmware.

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Attachments are accessible only for community members.

PaSw,

Attached is a modified App Note project that defines a Tx_Enable pin to control an external Bi-directional transceiver.

This Tx_Enable pin is enabled in the component configuration under the "Advanced" tab.

Len_CONSULTRON_0-1646697320775.png

Then you also have to declare the PSoC GPIO pin to use for this signal in the "DWR/Pins" window.

Len_CONSULTRON_1-1646697409361.png

I hope this helps.

Len
"Engineering is an Art. The Art of Compromise."
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This example shows a full duplex connection, I only have half duplex (a single output pin for RX and TX). The TX_EN is working fine, I have no issue with that. My RX and TX terminals are connected to a bufoe component controlled by the TX_EN, this all works fine for the UDB UART, but the issue is that the UART SCB has fixed RX and TX connections and it won't allow me to route to a single bidirectional pin.  

As I mentioned earlier I have an identical setup to the first post in the thread I originally linked, and the same problem they had.  According  to that thread their problem was resolved but the actual resolution is not provided. I posted this to try and clarify what their resolution is as it is apparently possible (or else that thread is mislabeled as resolved).

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PaSw,

... My RX and TX terminals are connected to a bufoe component controlled by the TX_EN, this all works fine for the UDB UART, but the issue is that the UART SCB has fixed RX and TX connections and it won't allow me to route to a single bidirectional pin.  


You are correct.   On the PSoC6s (and later PSoC4s) Cypress elected to reduce the GPIO functionality of the Digital Routing 'Fabric'.  options.   From my research, I cannot find a way for a GPIO to be assigned to be Bidirectional or as a Input and Output pin with Output enable.

Unless someone can show how a GPIO pin can be configured as listed above, you have to assign a separate pin for Input and for an Output as open drain and physically connect the pins together outside the IC.

The TopDesign allows for a "BiDirectional" and a Input/Output with OE, but I have yet to get either of these GPIO configurations to route and build.   It these GPIO types are not allowed, Infineon should remove them from the component catalog for the PSoC6.

I have two solutions that do route.

Solution #1

Len_CONSULTRON_0-1646835834627.png

This solution has the advantage of eliminating the Tx_oe control from the UART.   However, it basically requires a pullup on the GPIO.  I configured the Rx input as an digital input with Pullup.  This eliminated an external pullup resistor.    

The potential downside is the data rate.  Since the Tx output is open drain, it pulls low strongly but an inactive high is a float.  The the float high is dependent on the value of the pullup resistor.   A lower value a faster float high.

Solution #2

Len_CONSULTRON_1-1646836185676.png

This solution theoretically could have faster data rates since the external transceiver IC can switch the driver off and the receiver on faster.

The downside is that it requires the Tx_oe signal through a GPIO to control the transceiver direction.

As I mentioned earlier I have an identical setup to the first post in the thread I originally linked, and the same problem they had.  According  to that thread their problem was resolved but the actual resolution is not provided. I posted this to try and clarify what their resolution is as it is apparently possible (or else that thread is mislabeled as resolved).

It was my "solution" that was apparently selected as "solved" on the thread you posted.   However,  sometimes solutions are accepted by the forum moderator and not the original person posting.   Therefore it is not clear which idea in the discussion that was adopted and working.

The solutions I list above do build/route.   Due to the internal architecture of the PSoC6, it is much more limited than what is available on the PSoC5.

 

Len
"Engineering is an Art. The Art of Compromise."
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