GPIO, routing

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What is Smart IO and GPIO_OVT?

Can I connect internal periphery to any pins like at PSoC 5 or some pin are fixed like at PSoC 4?


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A 5V tolerant PSoC 6 is also in the plan. The 3.6 V limit was a trade-off we had to do for the first 40 nm PSoC.

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Smart I/O - These blocks provides the ability to perform Boolean functions in the I/O signal path. You can refer to TRM of PSoC 4000S/4100S and Analog Co-processor for details on the same. It is part of the IO system chapter in the TRM. If you want to learn how to use Smart I/O in PSoC Creator, you can refer to PSoC Creator Smart I/O Component (available in PSoC Creator 4.0+).

GPIO_OVT - These are Overvoltage Tolerant IOs, which means you can interface these IOs to voltages higher than chip VDDIO/VDDD/VDDA operating voltage. But care should be taken not to exceed the maximum operating voltage of the device (for PSoC 6 it is 3.6 V). For instance, say you are operating all the voltage domains of PSoC at 1.8 V and there are some signals that are in a 3 V domain. You can interface such IOs to the GPIO_OVT capable IOs. Again, you can use VDDIO for that purpose. OVT IOs are useful in chips/packages that do not support VDDIO or scenarios where you dont want all the IOs on the VDDIO to operate from the 3 V supply.

The internal periphery routing is similar to PSoC 4 (i.e. fixed). That said, with the amount of peripherals on-chip, this limitation may not arise for most use cases. For instance, with 9 SCBs on-chip, there is a SCB (I2C/SPI/UART) connection available on pretty much all the ports/pins.

Thank you.

It's a shame. I was hoping PSoC6 will 5 V.

In future PSoC7 or FM7 probably will not have a 5 V supply?


A 5V tolerant PSoC 6 is also in the plan. The 3.6 V limit was a trade-off we had to do for the first 40 nm PSoC.

Not applicable

3.3 (3.6 max) no problem.  I used to be set on 5V logic too.  It is more important to increase number of UDBs to match 5LP or greater.

Just use level shifter or voltage div. it if you want to continue 5V