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GaryLim
Employee
Employee
10 questions asked First like received 10 replies posted

Using MTB 3.0, starting from the Dual-CPU_IPC_Semaphore example, I am trying to implement some codes in CM0+. However, during compilation there is an error stating that my flash memory region is overflow. Please advise how can I make the memory adjustment. Thanks!

 

Compile Output:

Generating compilation database file...
-> ./build/compile_commands.json
Compilation database file generation complete
Building 203 file(s)
Linking output file proj_cm0p.elf
c:/users/XXXXXX/modustoolbox/tools_3.0/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: C:/Users/XXXXXX/mtw3/Dual-CPU_IPC_Semaphore/proj_cm0p/build/APP_CY8CPROTO-063-BLE/Debug/proj_cm0p.elf section `.text' will not fit in region `flash'
c:/users/XXXXXX/modustoolbox/tools_3.0/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: region `flash' overflowed by 21660 bytes
collect2.exe: error: ld returned 1 exit status
make[4]: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/build.mk:435: C:/Users/XXXXXX/mtw3/Dual-CPU_IPC_Semaphore/proj_cm0p/build/APP_CY8CPROTO-063-BLE/Debug/proj_cm0p.elf] Error 1
make[3]: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/main.mk:376: secondstage_build] Error 2
make[2]: *** [C:/Users/XXXXXX/ModusToolbox/tools_3.0//make/application.mk:72: build] Error 2
make[1]: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/build.mk:314: build_application_bootstrap] Error 2
make: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/main.mk:376: secondstage_build] Error 2
"C:/Users/XXXXXX/ModusToolbox/tools_3.0/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_IDE_TOOLS_DIR=C:/Users/XXXXXX/ModusToolbox/tools_3.0 CY_IDE_BT_TOOLS_DIR= -j8 all" terminated with exit code 2. Build might be incomplete.

Regards,

Gary

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1 Solution
jaholmes
Level 3
Level 3
First solution authored 10 sign-ins First like received

Hi, Gary - I ran into this recently myself when implementing USB CDC in the CM0+.  Happily, the instructions for growing the CM0+ flash allocation are in a comment at the top of system_psoc6.h.  Unhappily, those instructions are broken in MTB 3.0, at least for all the dual-CPU examples I've tried.  Here's what you actually do:

First, go to the CM0+ Makefile and delete or comment out the following line.  This line is added in MTB 3.0 for some reason, and makes the definition in system_psoc6.h redundant, breaking the instructions in that file:

 

DEFINES+=CY_CORTEX_M4_APPL_ADDR=CY_FLASH_BASE+0x4400U

 

Next, assuming you're using GCC, go to bsps\TARGET_APP_CY8CPROTO-063-BLE\COMPONENT_CM0P\TOOLCHAIN_GCC_ARM\linker.ld and grow the flash LENGTH from 0x4400  (or whatever it happens to be) to the desired value:

 

    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x4400

 

Tweak the same value in bsps\TARGET_APP_CY8CPROTO-063-BLE\COMPONENT_CM4\TOOLCHAIN_GCC_ARM\linker.ld:

 

FLASH_CM0P_SIZE  = 0x4400;

 

And again in bsps\TARGET_APP_CY8CPROTO-063-BLE\system_psoc6.h (this edit is prescribed in the instructions, but has no effect unless you first fix the Makefile as described above):

 

#if !defined (CY_CORTEX_M4_APPL_ADDR)
	#define CY_CORTEX_M4_APPL_ADDR          (CY_FLASH_BASE + 0x4400U)
#endif /* (CY_CORTEX_M4_APPL_ADDR) */

 

Rebuild everything and you should be good.

I posted about the Makefile bug a few days back but didn't get any official acknowledgement.  I can only assume that there aren't many people messing with the CM0+ halves of these samples.

Best,
Aaron

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2 Replies
jaholmes
Level 3
Level 3
First solution authored 10 sign-ins First like received

Hi, Gary - I ran into this recently myself when implementing USB CDC in the CM0+.  Happily, the instructions for growing the CM0+ flash allocation are in a comment at the top of system_psoc6.h.  Unhappily, those instructions are broken in MTB 3.0, at least for all the dual-CPU examples I've tried.  Here's what you actually do:

First, go to the CM0+ Makefile and delete or comment out the following line.  This line is added in MTB 3.0 for some reason, and makes the definition in system_psoc6.h redundant, breaking the instructions in that file:

 

DEFINES+=CY_CORTEX_M4_APPL_ADDR=CY_FLASH_BASE+0x4400U

 

Next, assuming you're using GCC, go to bsps\TARGET_APP_CY8CPROTO-063-BLE\COMPONENT_CM0P\TOOLCHAIN_GCC_ARM\linker.ld and grow the flash LENGTH from 0x4400  (or whatever it happens to be) to the desired value:

 

    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x4400

 

Tweak the same value in bsps\TARGET_APP_CY8CPROTO-063-BLE\COMPONENT_CM4\TOOLCHAIN_GCC_ARM\linker.ld:

 

FLASH_CM0P_SIZE  = 0x4400;

 

And again in bsps\TARGET_APP_CY8CPROTO-063-BLE\system_psoc6.h (this edit is prescribed in the instructions, but has no effect unless you first fix the Makefile as described above):

 

#if !defined (CY_CORTEX_M4_APPL_ADDR)
	#define CY_CORTEX_M4_APPL_ADDR          (CY_FLASH_BASE + 0x4400U)
#endif /* (CY_CORTEX_M4_APPL_ADDR) */

 

Rebuild everything and you should be good.

I posted about the Makefile bug a few days back but didn't get any official acknowledgement.  I can only assume that there aren't many people messing with the CM0+ halves of these samples.

Best,
Aaron

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GaryLim
Employee
Employee
10 questions asked First like received 10 replies posted

Hello Aaron,

 

Kudos and many thanks for providing the solution.  I have managed to overcome the flash size limitation.

Just to add a side note here, during my process of adjusting the flash size for CM0+, there seem to be a requirement for the flash size to be 1024 bytes aligned. Otherwise, the ASSERT will be set to false.

CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);

Apart from that minor adjustment, following your instructions will get the flash memory layout successfully re-organized and execute larger codes in CM0+ core.

 

Thanks!

Gary