Flash memory modification and debugging with CY8C6245

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schuetziken
Level 2
Level 2
First solution authored 5 replies posted 10 sign-ins

Hello,

I work with ModusToolbox via VSCode. I have successfully tested my programme on the CYPROTO-063-BLE kit. To do this, I had to adapt the flash memory there. Now I would like to run the same programme code on the CY8C6245, but I have the problem that the linker files are structured a little differently. For example, the following programme section is missing in the linker file of CM4:

/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x20000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;

Furthermore, I have already tried to change the origin of the flash memory, but then the multicore debugging no longer works.
In the appendix you can find some pictures of the working programme code for the CYBLE.
My question would be what exactly I have to change for the CY8C6245.

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1 Solution
schuetziken
Level 2
Level 2
First solution authored 5 replies posted 10 sign-ins

Hi @Rohan136 ,

as mentioned before I work with ModusToolbox via VSCode. 

The flash and RAM memory must be adjusted in certain cases. This is done in the linker.ld files. These files can be found under "Project → bsps → TARGET... → COMPONENT_... → TOOLCHAIN_GCC...". There is one file for each core.
The flash memory and its allocation to the respective core depends on the total memory capacity of the respective µC. Check the data sheet beforehand and then allocate the memory space as required.
If the flash memory space of CM0p is increased, the FLASH_CM0P_Size must also be adjusted in CM4 and the size must also be adjusted in the Makefile of CM0p under DEFINES. Important is that the position of the FLASH_CM0P_Size in the linker file depends on the µC!

== Example for  PSoC CYBLE-416045-02 ==

/*Example Linker File CM0p*/
MEMORY
{
      ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x03000
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x20000
}

/*Example Linker File CM4*/
MEMORY
{
      ram (rwx) : ORIGIN = 0x08003000, LENGTH = 0x044800
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
}

/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x20000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;

/*Example Makefile CM0p*/
# Add additional defines to the build process (without a leading -D).
DEFINES+=CY_CORTEX_M4_APPL_ADDR=CY_FLASH_BASE+0x20000U

== Example PSoC CY8C6245LQI-S3D42 ==

/*Example Linker File CM0p*/
MEMORY
{
      ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x1F000
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x20000
}

/*Example Linker File CM4*/
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x20000;

MEMORY
{
      ram (rwx) : ORIGIN = 0x0801F000, LENGTH = 0x1F000
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x5F000
}

If the size and start address of the flash memory of CM0p are specified in the linker file of CM4, then under no circumstances adjust the start address of the flash memory of CM4 in the linker file, as in the PSoC Creator, then the multi-core debug will no longer work.

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4 Replies
Rohan136
Moderator
Moderator
Moderator
100 replies posted 25 solutions authored 10 likes received

Hi @schuetziken ,

I didn't understand your question clearly, Can you elaborate more on what is the issue? Why are you changing the origin of the flash?

 

Regards,

Rohan

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schuetziken
Level 2
Level 2
First solution authored 5 replies posted 10 sign-ins

Hi @Rohan136 ,

thank you for your answer.

The case has now been fixed. I solved the problem yesterday. 

Kind regards

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Rohan136
Moderator
Moderator
Moderator
100 replies posted 25 solutions authored 10 likes received

Hi @schuetziken ,

 

Can you share your solution so that others facing the issue can refer to the solution?


Regards,

Rohan

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schuetziken
Level 2
Level 2
First solution authored 5 replies posted 10 sign-ins

Hi @Rohan136 ,

as mentioned before I work with ModusToolbox via VSCode. 

The flash and RAM memory must be adjusted in certain cases. This is done in the linker.ld files. These files can be found under "Project → bsps → TARGET... → COMPONENT_... → TOOLCHAIN_GCC...". There is one file for each core.
The flash memory and its allocation to the respective core depends on the total memory capacity of the respective µC. Check the data sheet beforehand and then allocate the memory space as required.
If the flash memory space of CM0p is increased, the FLASH_CM0P_Size must also be adjusted in CM4 and the size must also be adjusted in the Makefile of CM0p under DEFINES. Important is that the position of the FLASH_CM0P_Size in the linker file depends on the µC!

== Example for  PSoC CYBLE-416045-02 ==

/*Example Linker File CM0p*/
MEMORY
{
      ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x03000
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x20000
}

/*Example Linker File CM4*/
MEMORY
{
      ram (rwx) : ORIGIN = 0x08003000, LENGTH = 0x044800
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
}

/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x20000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;

/*Example Makefile CM0p*/
# Add additional defines to the build process (without a leading -D).
DEFINES+=CY_CORTEX_M4_APPL_ADDR=CY_FLASH_BASE+0x20000U

== Example PSoC CY8C6245LQI-S3D42 ==

/*Example Linker File CM0p*/
MEMORY
{
      ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x1F000
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x20000
}

/*Example Linker File CM4*/
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x20000;

MEMORY
{
      ram (rwx) : ORIGIN = 0x0801F000, LENGTH = 0x1F000
      flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x5F000
}

If the size and start address of the flash memory of CM0p are specified in the linker file of CM4, then under no circumstances adjust the start address of the flash memory of CM4 in the linker file, as in the PSoC Creator, then the multi-core debug will no longer work.

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