Fail to access Psoc6 BLE register "CYREG_BLE_BLELL_SCAN_CONFIG" to config BLE scan channel map

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eggheady
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Hi there:

Now I am using  following device and IDE to develop my BLE application with uart DFU and EEPROM usage

IDE: Psoc creator 4.4

PDL : 3.1.3

MCU : cyble-416045-02 

I want to scan advertise data on channel 37 only,

so I refered to this link and KBA218992 and try to config register "CYREG_BLE_BLELL_SCAN_CONFIG" in "cy_ble_evt_stack_on" event.

my code is list below(executed in CM4):

 

#define CYREG_BLE_BLELL_SCAN_CONFIG_USER (*(uint32*) CYREG_BLE_BLELL_SCAN_CONFIG)

void CentralEventHandler(uint32 event, void *eventParam)
{

     switch (event) {
     case CY_BLE_EVT_STACK_ON:
           CYREG_BLE_BLELL_SCAN_CONFIG_USER=CYREG_BLE_BLELL_SCAN_CONFIG_USER & 0xFFFF2FFF;
          break;

     ...other code

     }

}

 

but when I run my program to this line, MCU will get into "Cy_SysLib_ProcessingFault" function in "cy_syslib.c".

the most bothering thing is that ,

when I try to read the value  by "CY_GET_REG32(CYREG_BLE_BLELL_SCAN_CONFIG)" ,

the MCU also step into "Cy_SysLib_ProcessingFault"

the address of CYREG_BLE_BLELL_SCAN_CONFIG is defined in "cy_device_trm.h" with value "0x403c11d8u"

I also noticed that when I try to peer the memory value through memory window in debug mode,

the window will not show the value after BLE_BASE

(here we can see the ble_base address is 0x403c0000,and the memory window shows "## ## ## ##" after the that!

eggheady_0-1624444113637.png

I wonder if there are some constrains or condition to fulfill before access BLE related register? 

Can anyone give me some hint or suggestion? 

 

Anyway,thanks for your reading!

 

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1 Solution
VenkataD_41
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi, 

We found out the issue. The M0+ deep sleep and the CYREG_BLE_BLELL_SCAN_CONFIG register write in M4 are interlinked.

To access the “CYREG_BLE_BLELL_SCAN_CONFIG” register you need the BLE ECO. But when the controller (M0+) enters deep sleep, it turns off the ECO. And hence the access to the register is a fault.

Since you are using BLE in Dual-core (Controller in CM0+ and Host in CM4), to solve the issue you can and should modify this register in the controller (which actually handles the BLELL) and not host (M4). So you can move this register write to main_cm0p.c or corresponding files after the call Cy_BLE_Start(NULL);

Hope this information helps! Kindly check and update.

Thanks and regards

Ganesh

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10 Replies
VenkataD_41
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi,

I used the same firmware flow you have followed and it is working at our side. Please find the attached screenshot.

I am attaching the project we have used for testing on our side. Please test it at your end too and update us on the results.

If the attached project is not working at your side, there might be some problem with your schematic.

Thanks

Ganesh

 

Hi  Ganesh

Appreciate for your reply,

I've done the following modification to your attachment to fit the setup of my own project

1. change BLE module CPU core from single(complete component ion CM4) to dual core

2. modify cydwr interrupt config

3. modify code in main_cm0p.c

4. change device to cyble_416045_02 

and it works  

eggheady_3-1624528507263.png

the project i modified is in attachment,

if you need more information ,please let me know,

Thanks for your kindly helps again!

 

 

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VenkataD_41
Moderator
Moderator
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750 replies posted 500 replies posted 250 solutions authored

Hi,

Great! I have tested your project and it is working fine without any issues.

Regards

Ganesh

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Hi Ganesh :

Sorry for misleading you before,

but it doesn't solve my problem yet,

what I did is to modify the project you attached,

and it works fine with the BLE configuration of my project,

but the problem in my project is still happening,

I attach my project as attachment,

and please refer to "SDK1P-AM-000.cywrk" in "\BLEScanConfigIssue.zip\SDK1P-AM\SDK1P-AM.cydsn\" 

I really want to know what I can do to make it correct.

Thanks for your kindly helps!

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VenkataD_41
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi,

In your main_cm0p file of the Application project, please change the line Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR); to 

Cy_SysEnableCM4((uint32_t)(&__cy_app_core1_start_addr)); and I hope it solves the issue. I converted the sample code I sent you before into the UART-based DFU project and tested it. It is working fine. 

Can you please check the attached project? I am facing some issues with your attached project while doing the OTA. So I used my own project to test the issue you are facing.

Thanks

Ganesh

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Hi Ganesh :

I change the line you mentioned in main_cm0p.c file to 

Cy_SysEnableCM4((uint32_t)(&__cy_app_core1_start_addr)) ,but it doesn't works! 

I made some change to my project and write a demo document to demonstrate how my project works

please refer to "MyProject_demo.pdf" 

eggheady_0-1624618272373.png

and the project will show following message if you program "AM_Merged.hex" into device,

eggheady_2-1624618709505.png

 

if you need more information,please let me know

Thanks and regards

Will

 

 

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VenkataD_41
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi,

Thank you for the detailed project. When I removed the DeepSleep API call from main_cm0p of application, removed some delays which I felt unnecessary (as per my present understanding), and adding a few more CyBLE_ProcessEvents() calls, I made your project working. Please check the attached project.

I will let you know the issue with the DeepSleep API call asap.

Please check the attached project and image and let me know if it fails to work on your side.

Thanks and regards

Ganesh

Hi Ganesh :

Appreciate for your reply!

I removed " Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);" in main_cm0p.c as you mentioned ,

but keep other code unchanged in the project I attached(SDK1P-AM_02.zip),

and the result looks fine,

eggheady_0-1624848988736.png

but In my project, I need to implement deep sleep mode for both CPU  to reduce power consumption,

So I still need to find a way to put core0 into deep sleep mode, 

I know you've been working on it , and it really helps a lot, thank you!

If you need more information for debugging, please let me know

Thanks and regards!

 

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VenkataD_41
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi, 

We found out the issue. The M0+ deep sleep and the CYREG_BLE_BLELL_SCAN_CONFIG register write in M4 are interlinked.

To access the “CYREG_BLE_BLELL_SCAN_CONFIG” register you need the BLE ECO. But when the controller (M0+) enters deep sleep, it turns off the ECO. And hence the access to the register is a fault.

Since you are using BLE in Dual-core (Controller in CM0+ and Host in CM4), to solve the issue you can and should modify this register in the controller (which actually handles the BLELL) and not host (M4). So you can move this register write to main_cm0p.c or corresponding files after the call Cy_BLE_Start(NULL);

Hope this information helps! Kindly check and update.

Thanks and regards

Ganesh

Hi Ganesh :

Glad to see your reply,

I tried your solution and it works!

Thanks for the solution and detailed explanation!

It really helps!

Thanks and Regards!

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