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Hello, World!
I have a PSoC 6 project with one working SPI block and need to create a second. At least I think I do (one chip uses CPHA=1, CPOL=0 and the other uses CPHA=0, CPOL=0). When I add the second SPI block, I get the following:
Elaborating Design...
HDL Generation...
Synthesis...
Tech Mapping...
Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWCLK_TCLK(0) at location P6[7] prevents usage of special purposes: SCB[6].uart_cts. (App=cydsfit)
Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWCLK_TCLK(0) at location P6[7] prevents usage of special purposes: SCB[6].spi_select[0]. (App=cydsfit)
Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWCLK_TCLK(0) at location P6[7] prevents usage of special purposes: SCB[8].spi_select[0]. (App=cydsfit)
Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWDIO_TMS(0) at location P6[6] prevents usage of special purposes: SCB[6].uart_rts. (App=cydsfit)
Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWDIO_TMS(0) at location P6[6] prevents usage of special purposes: SCB[6].spi_clk. (App=cydsfit)
Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWDIO_TMS(0) at location P6[6] prevents usage of special purposes: SCB[8].spi_clk. (App=cydsfit)
Analog Placement...
Error: fit.M0059: FFB and IO placement failed: Failed to find a valid placement for \SPI_2:SCB\. (App=cydsfit)
Dependency Generation...
Cleanup...
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
--------------- Rebuild Failed: 11/30/2022 00:22:46 ---------------
I think the problem is rooted in the info messages, but I am still a noob and don't really understand what's going on.
I am using a Pioneer board and have 1 x I2C, 2 x SPI, and some analogs. I tried to choose pins that I can get at from the Pioneer's headers.
I2C_1:scl P6[0] pin K8
I2C_1:sda P6[1] pin J8
SPI_1:miso_m P12[1] pin B4
SPI_1:sclk_m P12[2] pin C4
SPI_1:s0_m P12[3] pin A3
SPI_2:miso_m P5[1] pin K6
SPI_2:mosi_m P5[0] pin L6
SPI_2:sclk_m P5[2] pin J6
SPI_2:s0_m P5[3] pin K7
UART:rx P11[0] F5
UART:tx P11[1] E5
AIN0 P10[0] B8
...
AIN5 P10[5] B7
I am using P6[0] and P6[1] but not P6[7] or P6[6]. Can I not use anything on P6?
In a nutshell, I'm trying to use as many of the Arduino header pins as I can but am willing to connect to any pin that makes the project work.
Any thoughts?
Thanks in advance!
Peter
Solved! Go to Solution.
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I have been playing around with this quite a bit. If I let PSoC Creator (4.4) auto-generate the pin assignments, it will find a combination of pins that accommodates all of the blocks (SPI1, SPI2, I2C1, UART). However, it picks pins that are not available on any of the headers on the Pioneer board - so I can not use them for my prototype. I have tried lots of different combinations of pins manually, to no avail.
Is there a feature somewhere in the IDE that would allow me to tell which pins are (not) usable for auto-assignment?
Other than that, fortunately one of my SPI chips also supports I2C, which eliminates the need for one of the SPIs (solving my problem).
Edited to add that I don't fault of the Pioneer kit. It's a great board with a lot of functionality for prototyping and getting used to the PSoC's features. I think that the designers of the board made good choices trading features like number of headers/pins for size and cost.
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I have been playing around with this quite a bit. If I let PSoC Creator (4.4) auto-generate the pin assignments, it will find a combination of pins that accommodates all of the blocks (SPI1, SPI2, I2C1, UART). However, it picks pins that are not available on any of the headers on the Pioneer board - so I can not use them for my prototype. I have tried lots of different combinations of pins manually, to no avail.
Is there a feature somewhere in the IDE that would allow me to tell which pins are (not) usable for auto-assignment?
Other than that, fortunately one of my SPI chips also supports I2C, which eliminates the need for one of the SPIs (solving my problem).
Edited to add that I don't fault of the Pioneer kit. It's a great board with a lot of functionality for prototyping and getting used to the PSoC's features. I think that the designers of the board made good choices trading features like number of headers/pins for size and cost.