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PSoC™ 6 Forum Discussions

DaBr_659386
Level 3
Level 3
10 replies posted 10 questions asked 5 replies posted

Hi,

I'm trying to get ETM trace working on a CY8CKIT-062-BLE PSoC® 6 BLE Pioneer board using ModusToolkit with a modified version of the 'Blinky' project. I've selected ETM in the Debug section of Device Configurator to configure the 5 GPIO lines and then added custom code (to the M4 project) to set-up the TPIU and ETM registers as per the ARM data sheets. Currently all trace lines are driven low.

By digging around I found that the TPIU base address is located at 0xE008E000 and not the usual 0xE0040000. I suspect there may be some additional undocumented steps I need to take to get trace working such as enabling a clock, etc. Perhaps the cross trigger interface also needs to be configured but there's nothing in the documentation about this.

Has anyone got ETM trace working on a PSoC6 processor or is there an app note available ?

Thanks

Dave

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1 Solution

My test project and salesae logic analyzer capture file all attached. My IAR version is 8.32.4, j-link software pack version is 6.44

3.JPG

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14 Replies
Vison_Zhang
Moderator
Moderator
Moderator
250 solutions authored 10 likes given 500 replies posted

First, data[0] should be assigned to P9[3] not P7[7], please confirm this configuration is correct.

Second, please help provide below info:

ModusToolsBox IDE Version:_____

Hardrware Tool:_____

Firmware version of Hardware Tool:_____

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VisonZ_71

Here is the information you requested:

1. Data[0] is configured for P9[3]

2. ModusToolsBox IDE Version: v1.1.0

3. Hardware Tool: custom

4. Firmware version of Hardware Tool: N/A

The ETM trace tool has been used with parts from a number of other manufacturers with no problems once the I/O and any relevent clock has been configured. The CY8C6347 I/O appears to be set-up correctly but the fact there's no activity on any of the 5 trace signals, especially trace clock, suggests that I'm missing an additional (non-standard) step e.g. clock, a dual-core related setting, etc.

Any suggestions ?

Thanks

Dave

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OK, I've got a bit further with configuring ETM.

As I suspected, there's a clock that needs to be enabled (cpuss.clock_trace_in). I assigned it an 8-bit divider clock configured as divide-by -1. I now have two issues:

1) The modified example I'm using has a 144MHz CPU clock and the trace clock is 36MHz suggesting the trace clock is CPU clock /4 not /2. Is this expected ?

2) With the TPIU, ETM, DWT registers configured for ETM tracing, all I get is the 7f-ff-ff-ff sync sequence on the 4-bit trace port when the M4 CPU is running. It looks like  ETM tracing is not enabled and may have something to do with needing to configure the ECT module.

Cypress, do you have any documentation that will help configure PSocC6 ETM trace operation ? There's nothing in the various data sheets. Please don't say go check the ARM documents!

Thanks

Dave

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Can anyone from Cypress offer any suggestions please ?

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Please try to place the below code in main() function, see if can help get the trace data successfully.

Cy_SysClk_PeriphAssignDivider(PCLK_CPUSS_CLOCK_TRACE_IN, CY_SYSCLK_DIV_16_BIT, 0u);

Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, 0u);

Cy_SysClk_PeriphEnablePhaseAlignDivider(CY_SYSCLK_DIV_16_BIT, 0u, (cy_en_divider_types_t)0x03, 63);

VisonZ_71,

Thanks for the suggestion. However, this gives exactly the same results as I already achieved i.e. 7f-ff-ff-ff sync sequence on the 4-bit trace port and a 36MHz trace clock.

Please let me know if you can answer the following questions:

1) The modified example I'm using has a 144MHz CPU clock and the 36MHz trace clock suggests that on the PSoC6, the trace clock is CPU clock /4 not /2. Is this expected ? (there's nothing in the documents about this)

2) I've configured the M4 TPIU, ETM, DWT registers as per the ARM data sheets. The continual 7f-ff-ff-ff sync sequence on the trace port, even when the M4 CPU is running, shows that although the port is basically configured tracing is not enabled. I'm guessing the embedded cross trigger module (ECT) needs to be set-up but with no information available in the PSoC6 data sheet or TRM it's very difficult to figure out how to configure it.  Assuming the ECT also needs setting-up, do you have any information on how to do this ?

The ARM data sheets are fairly generic and so it would need some info from Cypress as to how the ECT is configured in the PSoC6.

Thanks

Dave

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If you add code i provided in post#5 in main,c the trace clock is CPU clock /4, this is expected.

I cannot find doc which can explain how to enabled ETM trace function clearly, but i tested the ETM Trace function use IAR8.32 + J-link + CY8CKIT-062-BLE DVK, it works .  The frequency on Traceclk(P7[0]) is 25MHz(CPU core 100MHz, Clock_Peri 50MHz).

My Test code in IAR is very simple:

int main(void)

{

    __enable_irq(); /* Enable global interrupts. */

    Cy_SysClk_PeriphAssignDivider(PCLK_CPUSS_CLOCK_TRACE_IN, CY_SYSCLK_DIV_16_BIT, 0u);

    Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, 0u);

    Cy_SysClk_PeriphEnablePhaseAlignDivider(CY_SYSCLK_DIV_16_BIT, 0u, (cy_en_divider_types_t)0x03, 63);

    for(;;)

    {

          Cy_GPIO_Inv(BLED_PORT, BLED_NUM);

          CyDelay(1000);

    }

}

For ETM trace init of PSOC6, internal engineer wrote script file of J-link tool few days ago, i think it may also useful to you.

Thanks for your reply and for the script.

When you say ETM works with IAR8.32 + J-link + CY8CKIT-062-BLE, I assume you are not actually decoding data from the trace port ? (you're using a J-Link not J-Trace?)

If you are looking at the pins on the trace port on an oscilloscope, do you see activity on *all* trace data pins as well as trace clock ?

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Yes, i checked the signal of all four data pins use oscilloscope, i didn't decode data from trace port but i do see different high<-->low toggling signal on all four data pins.

I'm not seeing what you're getting.

Can you post your project so I can replicate what you get please ?

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My test project and salesae logic analyzer capture file all attached. My IAR version is 8.32.4, j-link software pack version is 6.44

3.JPG

Thanks for the project, I was able to get activity on the ETM lines using it.

I went back to my original project and found that I could also get ETM working using a J-Link rather than the integrated KitProg3. It seems that the J-Link is doing some additional configuration that the KitProg3 isn't.

Do you have any suggestions what the difference might be ?

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Dave, I don't think KitProg3 support embedded ETM trace debug feature.

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I don't think J-Link supports ETM directly but it seems to do something that KitProg3 doesn't that allows ETM to work when the TPIU, DWT & ETM registers are configured. I'll investigate further, maybe dump all relevant registers for differences.

Thanks for your help in trying to get to the bottom of this. It would be really helpful to add some more detail to the PSoC6 reference manual for the debugging sub-system, especially ETM trace. Basic omissions include max trace clock frequency being CPU clock / 4 and a block diagram of the dual CPU cross trigger.

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