How can a 64-bit doubleword register be enabled?
If -D16 implies DoubleWord capability, does PSoC 6's implementation of M4 support -D16?
Some implementations of ARM Cortex M4 claim FPv4-SP-D16.
I could not find FPv4-SP-D16, only FPv4-SP in any Infineon document.
- AN215656 PSoC™ 6 MCU dual-core system design @ https://www.infineon.com/dgdl/Infineon-AN215656_PSoC_6_MCU_Dual-CPU_System_Design-ApplicationNotes-v... mentions FPv4-SP
There's a comment in Arm Cortex-M4 Datasheet under the section, "Floating Point Unit (FPU) in the Cortex-M4 with FPU processor providing:" that implies a 64-bit double word register can be implemented by addressing multiple 32-bit registers as fewer 64-bit double-word registers,
"- 32 dedicated 32-bit single precision registers, also addressable as 16 double-word registers"
Greg
