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Hi Team,
We are designing with CY8C6247FDI-D32T.
The design has.
1*SPI - MISO - P6.1 - scb[8].spi_miso:0
MOSI - P6.0 -scb[8].spi _mosi:0
SCK - P6.2 - scb[8].spi _clk:0
CS - P6.3 - scb[8].spi_select0:0
2*ADC - P10.0, P10.1, P10.4, and P10.5
1*DAC - P9.2
8*PWM - PWM1 - P8.0 - tcpwm[0].line[0]:2
PWM2 - P8.2 - tcpwm[0].line[1]:2
PWM3 - P8.4 - tcpwm[0].line[2]:2
PWM4 - P11.4 - tcpwm[0].line[3]:3
PWM5 - P5.0 - tcpwm[0].line[4]:0
PWM6 - P12.2 - tcpwm[0].line[5]:3
PWM7 - P12.4 - tcpwm[0].line[6]:3
PWM8 - P5.6 - tcpwm[0].line[7]:0
2*I2C - I2C1 - SCL - P7.0 - scb[4].i2c _scl:1
SDA - P7.1 - scb[4].i2c_sda:1
I2C2 - SCL - P11.0 -scb[5].i2c _scl:0
SDA - P11.1 -scb[5].i2c_sda:0
3*UART - UART1 - RX - P1.0 - scb[7].uart _rx:0
TX - P1.1 - scb[7].uart_tx:0
UART2 - RX - P0.2 -scb[0].uart _rx:0
TX - P0.3 -scb[0].uart_tx:0
UART3 - RX - P12.0 -scb[6].uart _rx:0
TX - P12.1 -scb[6].uart_tx:0
SWD is the debugging interface. -
SWDIO - P6[6]
SWCLK - P6[7]
XRES
SWO - P6[4]
32KHz RTC OScillator - P0[0], P0[1]
Part Number - CM9V-T1A-32.768KHZ-12.5PF-20PPM-TA-QC
Load Capacitor 22pF
High-speed oscillator - P12[6], P12[7]
Part Number - LFXTAL063075BULK
Load Capacitor - 12pF
The schematic is attached herewith.
Please let me know if there are any mistakes.
Solved! Go to Solution.
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Hi @shibin,
I have reviewed the schematic and the following are my recommendations:
1) Insert 330 Ohm resistance in series with I2C lines before pullup of 4.7k Ohm.
2) You can remove 1uF capacitors from VDDA and VBACKUP. (If your application requires more filtering then you can keep it).
3) For VBUCK1 only a 4.7uF capacitor is required.
The remaining things are perfect.
Please, let us know if you need further clarification.
Thank you
Best Regards
Raj Chaudhari
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Hi @shibin,
I have reviewed the schematic and the following are my recommendations:
1) Insert 330 Ohm resistance in series with I2C lines before pullup of 4.7k Ohm.
2) You can remove 1uF capacitors from VDDA and VBACKUP. (If your application requires more filtering then you can keep it).
3) For VBUCK1 only a 4.7uF capacitor is required.
The remaining things are perfect.
Please, let us know if you need further clarification.
Thank you
Best Regards
Raj Chaudhari
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Hello Raj,
Thank you for your reply.
Updated the circuit as per your review comments.
Could you please explain what is a voltage mode DAC mentioned in the datasheet of CY8C6247FDI-D32T?.
As per the datasheet, "12-bit Digital-Analog Converter. There is a 12-bit voltage mode DAC on the chip, which can settle in less than 5 µs. The DAC may be driven by the DMA controllers to generate user-defined waveforms. The DAC output from the chip can either be the resistive ladder output (highly linear near the ground) or a buffered output."
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Hi Shbin,
We recommend you to create new threads on different topics so that it will be useful for other users who are searching the same topic on the forum. This will also help each thread to be topic specific. Now regarding your question, PSoC6 has a Digital to Analog converter. This can be used generate waveforms with help of a DAC. All you need is a array with the corresponding waveform values(within12 bit range) and DMA to periodically transfer it. Additionally the internal opamps can be used buffer the DAC output for better response. I hope this clears your doubt. Do let us know if we missed something.
Best Regards,
Vasanth
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Hello Raj.
The Pitch of CY8C6247FDI-D32T is very fine-pitched.
Are there any recommended fanout methods and via structures available so that we can follow them?.
If available can you please provide any reference design for this package?.
We are looking forward to hearing from you.
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Hi @shibin,
We don't have the reference design for the above MPN.
Please, let us know if you need further clarification.
Thank you
Best Regards
Raj Chaudhari