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Hello,
I need to create a square wave signal generator in the range of 1.5Mhz-1.8MHz, in resolution of 10KHz, by PSOC63
How do I do that ?
When I try to use the PWM timer I can't reach the frequency resolution I need.
I can set in the "TopDesign" HW configuration several clocks with the frequencies I need, but I can't change them by SW like I am expecting
What would be the best way to do that ?
THank,
Shy
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PSoC 6 MCU
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shhe,
I believe that it is possible to swipe PSoC63 output frequency in 1.5-1.8MHz by changing the PLL divider coefficient. For example, swiping the HFCLK (bus clock) in range 60-72MHz, and dividing it by 40. You should consider PLL settling time (~100us), which ultimately limits the swiping speed.
Check PLL API for manual setting of the fractional divider.
Please note that this is rather unusual mode of operation, as the bus frequency of the entire PSoC will ondullate, affecting other components, which depend on clock. But if the swiping generator is the only function PSoC performs, it should work.
/odissey1
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shhe,
I believe that it is possible to swipe PSoC63 output frequency in 1.5-1.8MHz by changing the PLL divider coefficient. For example, swiping the HFCLK (bus clock) in range 60-72MHz, and dividing it by 40. You should consider PLL settling time (~100us), which ultimately limits the swiping speed.
Check PLL API for manual setting of the fractional divider.
Please note that this is rather unusual mode of operation, as the bus frequency of the entire PSoC will ondullate, affecting other components, which depend on clock. But if the swiping generator is the only function PSoC performs, it should work.
/odissey1
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Hi,
Thank you for your reply
How do I do that ? how do I change the PLL divider coefficient ?
Thanks,
Shy
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Shy,
The API call to manually change the PLL is:
cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t * config )
Look for this function in the PDL docs under the SysClk section.
"Engineering is an Art. The Art of Compromise."