Consecutive I2C transactions fail with CY_SCB_I2C_MASTER_NOT_READY

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Panometric
Level 5
Level 5
100 sign-ins 100 replies posted 10 solutions authored

Device is CYBLE-416045-02, sometimes two consecutive I2C transactions fail. Happens with (Write then read)  and (Write then Write) cases. 

Pseudo code:

 

 

cy_stc_scb_i2c_master_xfer_config_t transfer;
uint8_t writeBuffer[1UL] = { subAddress };
transfer.slaveAddress = i2cAddress;
transfer.buffer       = writeBuffer;
transfer.bufferSize   = 1;
transfer.xferPending  = true; /* Do not generate Stop 
Cy_SCB_I2C_MasterWrite(SCB1, &transfer, context);
xSemaphoreTake(i2c_sem);// wait for CY_SCB_I2C_MASTER_WR_CMPLT_EVENT callback
Cy_SCB_I2C_MasterRead(); //returns CY_SCB_I2C_MASTER_NOT_READY

 

 

If CMPLT_EVENT was received, how can a master not be ready ?

I found if I wait 20uS after a MASTER_NOT_READY, it works. But I cannot explain why I need to waste that time. 

 

 

0 Likes
4 Replies
Aashita_R
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 250 replies posted

Hi @Panometric ,

Can you please let us know the pseudo code for this?

xSemaphoreTake(i2c_sem)

 

Also, is 20uS an absolute figure or have you tried with a range of wait time? This will help us understand the issue at the device level.

Best Regards,

Aashita

 

0 Likes
Panometric
Level 5
Level 5
100 sign-ins 100 replies posted 10 solutions authored

xSemaphoreTake(i2c_sem) is just the interrupt and callback. 

 

void I2C_Isr(void)
{
   Cy_SCB_I2C_MasterInterrupt(SCB6, t&i2cContext));
}
void I2C_Callback0(uint32_t events)
{
   BaseType_t xHigherPriorityTaskWoken;
   // Unblock the task by releasing the semaphore
   // only if I2C master read or write is completed
   if((events & CY_SCB_I2C_MASTER_WR_CMPLT_EVENT) 
   || (events & CY_SCB_I2C_MASTER_RD_CMPLT_EVENT))
   {
      xSemaphoreGiveFromISR(i2c_sem, &xHigherPriorityTaskWoken);
      portYIELD_FROM_ISR(pdTRUE);
   }
}

 


20uS seems to be enough with my bus running at 340 Khz, but not enough at 100 Khz. 

0 Likes
Panometric
Level 5
Level 5
100 sign-ins 100 replies posted 10 solutions authored

@Aashita_R can you follow up on this?

0 Likes
Panometric
Level 5
Level 5
100 sign-ins 100 replies posted 10 solutions authored

@Aashita_R It has been one month without a resolution.  Why would the callback get CY_SCB_I2C_MASTER_WR_CMPLT_EVENT yet after that happens, the next call gets  CY_SCB_I2C_MASTER_NOT_READY ?

0 Likes