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PSoC™ 6

Level 4
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Level 4

The architecture TRM shows the ALU ASRC mux in two different ways, and they leave me a bit unsure about what I can expect. In the overview section we have this:

Anmerkung 2020-09-07 095217.png

The above schematic would indicate that whenever PI is selected by SRC A, PO = PI. However, in the parallel in/out section, this schematic is used:

Anmerkung 2020-09-07 095124.png

This indicates that I can use PI as input to the ALU, perform an operation on it, and store the result in A0 or A1 for parallel output. Which is right?

My goal is to have the following instructions:

  • load A0 = D0; A1 = D1
  • PO = A0
  • PO = A1
  • PO = PI & A0
1 Solution
Level 4
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Level 4


I believe the schematic in the parallel in/out section is the right one (PO is a mux selection between A0 or A1), because the TRM of PSoC5LP (which have the same UDB architecture) has consistent representation both in overview section and parallel in/out section. Below is a screenshot of the datapath overview from page 168 of PSoC5LP TRM: https://www.cypress.com/file/123561/download

datapath top level diagram screenshot PSoC5LP TRM.jpg

and parallel in/out section in page 185 of PSoC5LP TRM

datapath parallel in_out diagram screenshot PSoC5LP TRM.jpg

Cypress may have to update the PSoC6 TRM document regarding the datapath overview diagram.

Best Regards,

Prem Sai

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