Clock settings PSOC6 for audio

[ravo]

Dears,

based on USB Audio Device (FreeRTOS) demo  I have more question regarding clock settings. I create rather new thread.

I am using PSOC6 (on CY8CPROTO-062-4343W kit). I would like to change CM4 clock to 150 MHz, because I need to speedup CM4 core. But I have problem with CLK_PERI which is used also to generate PWM 

PWM setup:

cyhal_pwm_t mclk_pwm;

cyhal_pwm_init(&mclk_pwm, (cyhal_gpio_t) P5_0, NULL);
cyhal_pwm_set_duty_cycle(&mclk_pwm, 50.0f, 18432);
cyhal_pwm_start(&mclk_pwm);

this is MCLK pin for I2S audio and must be synchronized with I2S audio LRCLK

I am able to set 150MHz for M4 code using PLL1 -  to generate 150MHz clock and route this to CLK_HF0 from CLK_PATH2, CLK_PERI (divider 2) -> 75Mhz. as shown here.

But PWM now is not synchronized with I2S Audio clock LRCLK 

Is there option to generate PWM from another source then CLK_PERI so that this two clocks could be synchronized and CM4 speed could be independent ? Can I used TCPWM? or another block as I normally use in PSOC Creator...

Thanks in advance, regards

Radim

But I would like to have CLK_HF0 independent on ext crystal to be able to run core M4 for 150 MHz

[RodolfoGL]

You could get very close to 150 MHz and keep the audio frequencies if you set:

For 48KHz:

- PLL: 147.456 MHz

-  CLK_HF1: 18.432 MHz

- CLK_FAST/CLK_PERI: 73.728 MHz

For 44.1KHz:

- PLL: 135.4752 MHz

-  CLK_HF1: 16.934 MHz

- CLK_FAST/CLK_PERI: 67.738 MHz

Note the PWM HAL uses the TCPWM underneath, so in this case, you need to make sure the CLK_PERI and CLK_HF1 (audio subsystem) are sourced by the same clock.

If you don't want to use a PWM, there are two ways:

- Use the i2s_if (P5.0) pin if your codec can generate the MCLK. In this case, the MCLK substitutes the CLK_HF1. (PMODI2S does not support this though)

- Use the CLK_HF5. This clock has a direct connection to the P0.5 pin.  You would need to some wiring to get this connection to the PMODI2S.

[ravo]

Dear @RodolfoGL,

very thanks for quick response. It will look very good. I will test these config, and write soon back.

Maybe in future I will use only 16kHz audio, because it is only for speech audio processing tasks... but 48kHz is preferable  

Regards and have a nice day.

Radim

[ravo]

Dear @RodolfoGL i just tested suggested settings.

Yes audio is played but with struggling  crackling noise.

I just tested on USB Audio Device (FreeRTOS) demo  project 

Did I need also change some defines ? e.g. PLL_FREQ_FOR_48KHZ or PLL_FREQ_FOR_44KHZ to adapt new CLK ? In audio_app.c are these definitions:

/*******************************************************************************
* Macros
********************************************************************************/
#define MI2C_TIMEOUT_MS 10u /* in ms */
#define MCLK_CODEC_DELAY_MS 10u /* in ms */
#define MCLK_FREQ_HZ 18432000u /* in Hz */
#define MCLK_DUTY_CYCLE 50.0f /* in % */
#define USB_CLK_RESET_HZ 100000 /* in Hz */
#define PLL_TIMEOUT_US 12000u /* in us */
#define PLL_FREQ_FOR_48KHZ 55296000 /* in Hz */
#define PLL_FREQ_FOR_44KHZ 50803200 /* in Hz */

I found that if I set #define PLL_FREQ_FOR_48KHZ 10248163 // lower value it will play normal. But I hope that  it should be 73728000 or maybe I am wrong.

Radim

Regards Radim

[ravo]

Dear @RodolfoGL 

Have you some news regarding clock settings for USB audio ?

Regards

Radim

[RodolfoGL]

Hi Radim,

You need to keep the PLL frequency to always 147.456 or 135.4752. So need to update the #define PLL_FREQ_FOR_48KHZ  and PLL_FREQ_FOR_44KHZ to these frequencies.

One thing I forgot to mention is to enable the ECO. This board has an ECO at 34.4064 MHz. Make sure to source the PLL from the ECO (instead of IMO).

The HFCLK1 (for the audio subsystem) should be less than 50 MHz, so set the divider to 4.

Let me know if the cracking sound is gone after these changes.

[ravo]

Dear @RodolfoGL ,

thanks for comments I found that when I set #define PLL_FREQ_FOR_48KHZ 10248163 (founded with iterations) Now it will work as expected without any sound artefacts.

I tested on both CY9CPROTO with ECO 34.4064 MHz and also with CY8CKIT-062WIFI-BT with ECO 17.203 MHz with this SYSTEM clock setup

PLL settings:

and CLK_HF1 146.227 MHz source as CLK_PATH1 - with divider 8 I get 18.278 MHz

and I must mention that I am not using WCO to ILO for 32kHz low speed clock

Radim

[RodolfoGL]

If you use ECO as 17.2032 MHz, you can't reach the exact frequency (147.456 or 135.4752). Has to be 34.4064 MHz. There is some limitation on the PLL parameters to achieve these frequencies.

I find odd you say that setting PLL_FREQ_FOR_48KHZ  to ~10MHz fixes your issue. Note that we are using the PLL to also drive the CPU, which means you are setting the CPU to run at around 10 MHz only (at least that is what the original code does). You want to keep the CPU running as fast you can (~147MHz or ~135MHz).

[ravo]

Dear @RodolfoGL ,

maybe I did not understand you correctly. In my settings clock for CM4 is 146.227 (CLK_FAST) - so I thought that this is on. But now found that in audio_app code is called

cyhal_clock_set_frequency(&pll_clock, PLL_FREQ_FOR_48KHZ, &tolerance_0_p);

So correct PLL is only about 10MHz as you mention.

So I think that I will need to change ECO to 34.4064 MHz... I will replace XTAL and get know if it helped me.

P.S1: Part number for 8Y34470001 from TXC, but it could not be bought and I am unable to find any replacement.

P.S2: I am thinking about change sample frequency to only 16kHz, can you provide me correct settings or where find how to recalculate the PLL settings for this sample freq. Maybe this is better way, because I am doing only voice application and there the 16kHz instead of 48kHz could be adequate. 

Thanks once more for your help

Radim

[ravo]

Dear @RodolfoGL 

I am still in trouble with CLOCK settings. Can you please wrote suggestion how to achieve as close as possible 150MHz MCU speed with I2S audio on 48 kHz and 16 kHz using 17.2032 MHz (I am now using CY8C6247BZI-D54 on custom HW based on CY8CKIT-062 WIFI-BT where was 17.203 MHz xtal) but connected to digilent "pmod i2s2" instead of I2S codec AK4954A on TFT shield)

Best regards

Radim

[RodolfoGL]

You would need an ECO of 34.4064 MHz to achieve 147.456 MHz in the PLL output.

If you use ECO of 17.2032 MHz, you can only reach up to 49.152 MHz. There is a limitation on the PLL parameters to achieve higher frequencies with a source of 17.2032 MHz.

[ravo]

Dear @RodolfoGL 

Thanks for answer. If I have a look at distributors I am unable to find 34.4064MHz. We are able to bought only 17.2032 MHz. No I have these config and CM4 is 55.296 MHz, where is 49.152 MHz ? And which PLL parameters do you mean ?

Best Regards Radim

[RodolfoGL]

I think for the PMOD I2S codec, you have to drive 32 cycles per word. If you can drive 24 cycles per word, then 55.296 MHz should be OK. 

The PLL has three parameters,  each of them can only be set within a range. 

• Feedback (22-122)
• Reference (1-18)
• Output (2-16)

The PLL output sourced by ECO formula is:

PLL Output = ECO x Feedback / Reference / Output

[ravo]

Dear @RodolfoGL,

I hope that I2S is setup with 32 bits ?  I did not do any modification in demo project USB Audio Device (FreeRTOS) demo or Am I mistaken ?

Yes I know these parameters ... I think that you mean something else

So limitation is that CLK_PERI and CLK_HF1 must be generated from same source ?

Radim

[RodolfoGL]

The default configuration on audio codec (AK4954a) is 24-bits per channel, that's why you see that frequency.

In the PMOD I2s - Slave mode, the table only shows SCLK/LRCK at 64, not 48, that's why I'm not so sure.

https://digilent.com/reference/pmod/pmodi2s2/reference-manual?redirect=1

If you use the CLK_HF5 as MCLK, instead of PWM, then you don't need to have the CLK_PERI sourced by the PLL. In your case, since you have only one PLL and one FLL, you can set the CLK_HF0/CLK_PERI to be 96 MHz and the PLL to whatever frequency you need (as 49.152 MHz or 55.295 MHz). 

[ravo]

Dear @RodolfoGL ,

I only modify makefile on line 84 I disable #COMPONENTS+=AK4954A to adapt source code (disable #ifdef COMPONENT_AK4954A sections in source code) and use PMOD I2S instead as default.

82: COMPONENTS=CUSTOM_DESIGN_MODUS FREERTOS
83: ifeq ($(TARGET), $(filter $(TARGET), CY8CKIT-062-WIFI-BT CY8CKIT-062S2-43012 CYW9P62S1-43012EVB-01 CYW9P62S1-43438EVB-01))
84: #COMPONENTS+=AK4954A
85: endif

I know this table from CS5343 datasheet, but it looks that multiplier 1152x is not supported, and your 1024x is OK (49.1520 MHz for MCLK).

Can you confirm that the demo has wrong MCLK setup ?

I would like try your suggestion use CLK_HF5 but this is not available on these device.

I did not understand "In your case, since you have only one PLL and one FLL, you can set the CLK_HF0/CLK_PERI to be 96 MHz and the PLL to whatever frequency you need (as 49.152 MHz or 55.295 MHz)" You mean CLK_HF0/CLK_PERI drive from FLL and from PLL MCLK ? But there I will not be synchronised MCLK with CLK_PERI, and audio will be corrupted.. I tried it before.

Best Regards

Radim

[RodolfoGL]

Sorry, the PSoC 6 you are using should be the CLK_HF4 (ext_clk).

Note that the MCLK frequency is different from the PLL frequency. You shall use the CLK_HF4 to divide the PLL frequency by 2 or 4.

If you use CLK_HF4 (ext_clk) instead of PWM, it doesn't matter. The PWM is sourced by CLK_PERI, but now you no longer need the PWM.

[ravo]

Dear @RodolfoGL ,

ok... I remember CLK_HF4 as you wrote earlier, but I can't use it because I don't have accessible P0.5  (G3 pad it is BGA) So I must find another solution. Maybe in future if we modify PCB board.

I now that MCLK is different from PLL (using dividers), but I suppose that must be synchronized with PWM / LRCLK ?

Do you have Idea why these settins ?

#define PLL_FREQ_FOR_48KHZ 55296000 /* in Hz */
#define PLL_FREQ_FOR_44KHZ 50803200 /* in Hz */

because both of them are out of range as noted in datasheet divider 1152 was it some reason to do it this way?

I tried to use lower MCLK (e.g. for 768x - can be 36.8640 MHz -> then PLL should be 4x as 147.456 MHz, but this could not be set. Is there any option to set PLL parameters manually ? Are there any PLL calculator ?

Or I found Infineon-AN218241_PSoC_6_MCU_Hardware_Design_Considerations-ApplicationNotes-v02_00-EN.pdf. on page 40:

Or e.g. I can go only for 16 kHz audio, because it is for speaking (like phone). Could this be better ?

Best Regards

Radim

[RodolfoGL]

To calculate the minimum CLK_HF1 frequency for the I2S, you can use this formula.

CLK_HF1 = Frame Rate X 16 X Channel Length

For channel length = 32, you get 48000 X 16 X 32 = 24.576 MHz

For channel length = 24, you get 48000 X 16 X 24 = 18.432 MHz

So you can pick a number multiple of these for CLK_HF1. That's where the 18.432 x 3 = 55.296 MHz come from. But you also need to consider what is the MCLK requirement for the audio codec. You should pick a number that satisfies both.

Dropping the frame rate might not help you to use a higher frequency for PLL, but you could use a lower frequency for MCLK.

If your application doesn't care much about the audio quality, you can try to use a frequency as close as possible of 147.456 MHz and see if it works. You will not be able to achieve 48KHz or 16KHz exactly, but it might be good enough for your application.

[ravo]

I tried set PLL to 147.456 MHz (system set close 148.378 MHz).

I update CLK_PERI divider = 2, and CYBSP_USB_CLK_DIV to 742 (for 100kHz)

but it did not work USB freezes and no sound.

Radim

[RodolfoGL · Accepted solution]

You are probably getting a hard fault. Try to run in debug mode to see where is crashing. The frequency set to the PLL/CLK_HF[0] should not affect the USB enumeration at all. Also set the clocks in the device-configurator, to avoid any firmware issue when dynamically changing the clocks, as the original CE does. 

Also double check what the init() function calls return, specially around the I2S when enforcing a given frame rate.

[ravo]

Dear @RodolfoGL ,

thanks I will check and try debug. Maybe I can step the initialization part of main and audio_app. But as I wrote in another thread https://community.infineon.com/t5/ModusToolbox-General/Expressions-in-Modus-Toolbox-3-0/m-p/395050 that I am unable to debug and view expressions in debug view in this application.

Best Regards

Radim

[ravo]

Dear @RodolfoGL ,

Now It look like that it is working for 16kHz audio. CM4 frequency is currently 148.378 MHz instead 147.456 MHz (for 16kHzi MCLK should be 6 441 000 Hz and PLL_FREQ_FOR_16KHZ 18432000) But I am unable to hear any differences... So now I can continue to work on audio projects. If I have another issue I will write back. But now we can close this "long" thread.

Many thanks to you.
Regards

Radim