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Hi,
I am using CYPROTO-060-4343w Evaluation board. I want to initialize capsense on CM0+ core and use it. When I initialize capsense on CM4 core, it works fine but for CM0+ it fails. I tried to debug and found out it fails at Cy_CapSense_SsAutoTune_Call(context); function during initialization. It returns value of 0x11.
I dont understand why does this happen. Same code works on one core and doesnt on other core. There is an option in Device Configurator to choose core for capsense, I selected CM0+, I have followed all the steps mentioned in AN215656 document to build dual core environment.
attaching project and configuration for reference.
Solved! Go to Solution.
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PSoC 6 MCU
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The issue is with the CapSense interrupt configuration. CapSense works on interrupts for scanning the sensors and the interrupt configuration is different for CM0+ and CM4. In the CapSense_Touch.c file, can you change your interrupt configuration to the following -
const cy_stc_sysint_t CapSense_interrupt_config =
{
.intrsrc=NvicMux2_IRQn,
.cm0psrc=CapSense_IRQ,
.intrPriority = CAPSENSE_INTR_PRIORITY,
};
Best regards,
Hari
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The issue is with the CapSense interrupt configuration. CapSense works on interrupts for scanning the sensors and the interrupt configuration is different for CM0+ and CM4. In the CapSense_Touch.c file, can you change your interrupt configuration to the following -
const cy_stc_sysint_t CapSense_interrupt_config =
{
.intrsrc=NvicMux2_IRQn,
.cm0psrc=CapSense_IRQ,
.intrPriority = CAPSENSE_INTR_PRIORITY,
};
Best regards,
Hari
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Hi,
That worked, Thanks
Rushikesh