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ChRe_4711096
Level 4
Level 4
50 replies posted 25 replies posted 25 sign-ins

I'd like to combine analog and digital on Port9. Can I

  • Use OA0 (P9.0, P9.1, P9.2) and the output of OA1 (P9.3) and
  • SCB2 

at the same time, using SmartIO to move the SCB2 signals from P9.0 and P9.1 to P9.4 and higher?

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1 Solution
ChRe_4711096
Level 4
Level 4
50 replies posted 25 replies posted 25 sign-ins

I managed to do what I asked for in the question. Here's the schematic:

ChRe_4711096_0-1630523055904.png

UART1 sends data to UART2, to have some data coming in through UART2's Rx input (Ch1 on the scope). The CPU just forwards that data through UART1's Tx output (Ch2 on the scope). Both UART2 pins are relocated from P9[0..1] to P9[4..5] using SmartIO. That frees GPIOs P9[0..1].

However, SmartIO consumes the free pins, so in order to use them they must be set to something else than "none" in the SmartIO configuration. The connected pins are configured to have both digital and analog connections. Those are connected to an internal OpAmp.

One OpAmp is configured as a buffer for the internal bandgap reference, and connected to P9[3]. This is used as negative input to the second OpAmp.

The second OpAmp is a comparator, with the positive input connected to an external potentiometer. The OpAmp's output is sent to a pin (scope Ch3). The output is either 0 or 3V3, depending on the potentiometer's position.

SmartIO used 4 LUTs, two each for each of the relocated pins:

ChRe_4711096_1-1630523843569.png

GPIO[0..1] are configured as (unused) inputs in order to get an external digital connection for the pins. The output mapping is 0xAA for all LUTs.

Main code (pretty dull but does the job):

int main(void)
{
  __enable_irq(); /* Enable global interrupts. */
  /* Enable CM4.  CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */
  Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR); 

  /* Place your initialization/startup code here (e.g. MyInst_Start()) */
  SmartIO_1_Start();
  UART_2_Start();
  UART_1_Start();
  Opamp_1_Start();
  VRef_Buffer_Start();
  for(;;)
  {
    /* Place your application code here. */
    // send character throgh UART2
    // receive through UART1
    // send through UART1 (to scope)
    if(1 == UART_1_Put(0x55))
    {
      uint32_t rx;
      while(1)
      {
        rx = UART_2_Get();
        if(rx != CY_SCB_UART_RX_NO_DATA)
        {
          UART_2_Put(rx);
          break;
        }
      }
    }
    Cy_SysLib_Delay(1);
  }
}

 

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3 Replies
ChRe_4711096
Level 4
Level 4
50 replies posted 25 replies posted 25 sign-ins

I tried something on the CYBLE-416045-02 and it seems that relocation of an SCB is pretty straight forward when it happens within the same nibble.

Schematic:

ChRe_4711096_0-1630492353403.png

SmartIO setup:

ChRe_4711096_1-1630492388738.png

The main code just starts SmartIO and the UART, and then goes into an endless loop of sending "U" (0x55) at 9600 baud:

int main(void)
{
    __enable_irq(); /* Enable global interrupts. */
    /* Enable CM4.  CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */
    Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR); 

    /* Place your initialization/startup code here (e.g. MyInst_Start()) */
      SmartIO_1_Start();
      UART_1_Start();
    for(;;)
    {
        /* Place your application code here. */
      UART_1_PutString("U");
      Cy_SysLib_Delay(2);
    }
}

Sending one character takes about 1 ms, but since PutString returns after that character has been placed in the FIFO, we need to insert a 2 ms delay between calls to get a 1 ms gap between two characters in the output.

Scope shot with channels as annoated in the schematic:

ds1054z-scope-display_2021-09-01_12-36-11.png

Getting the UART's Tx output to GPIO4 will not as simple because data1 can only be used as an input to LUT0...LUT3. However, it should be possible by routing LUT2's output to LUT4. I'll try that later today.

I also haven't made use of any analog features on P9[0..3] but that's something to try later, after I moved the SCB further up.

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ChRe_4711096
Level 4
Level 4
50 replies posted 25 replies posted 25 sign-ins

Another experiment - just like before I just moved the Tx pin, but to 9[4] this time. The SmartIO setup is this:

ChRe_4711096_2-1630519569507.png

So we need LUT1 and LUT4 this time.

 

0 Likes
ChRe_4711096
Level 4
Level 4
50 replies posted 25 replies posted 25 sign-ins

I managed to do what I asked for in the question. Here's the schematic:

ChRe_4711096_0-1630523055904.png

UART1 sends data to UART2, to have some data coming in through UART2's Rx input (Ch1 on the scope). The CPU just forwards that data through UART1's Tx output (Ch2 on the scope). Both UART2 pins are relocated from P9[0..1] to P9[4..5] using SmartIO. That frees GPIOs P9[0..1].

However, SmartIO consumes the free pins, so in order to use them they must be set to something else than "none" in the SmartIO configuration. The connected pins are configured to have both digital and analog connections. Those are connected to an internal OpAmp.

One OpAmp is configured as a buffer for the internal bandgap reference, and connected to P9[3]. This is used as negative input to the second OpAmp.

The second OpAmp is a comparator, with the positive input connected to an external potentiometer. The OpAmp's output is sent to a pin (scope Ch3). The output is either 0 or 3V3, depending on the potentiometer's position.

SmartIO used 4 LUTs, two each for each of the relocated pins:

ChRe_4711096_1-1630523843569.png

GPIO[0..1] are configured as (unused) inputs in order to get an external digital connection for the pins. The output mapping is 0xAA for all LUTs.

Main code (pretty dull but does the job):

int main(void)
{
  __enable_irq(); /* Enable global interrupts. */
  /* Enable CM4.  CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */
  Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR); 

  /* Place your initialization/startup code here (e.g. MyInst_Start()) */
  SmartIO_1_Start();
  UART_2_Start();
  UART_1_Start();
  Opamp_1_Start();
  VRef_Buffer_Start();
  for(;;)
  {
    /* Place your application code here. */
    // send character throgh UART2
    // receive through UART1
    // send through UART1 (to scope)
    if(1 == UART_1_Put(0x55))
    {
      uint32_t rx;
      while(1)
      {
        rx = UART_2_Get();
        if(rx != CY_SCB_UART_RX_NO_DATA)
        {
          UART_2_Put(rx);
          break;
        }
      }
    }
    Cy_SysLib_Delay(1);
  }
}

 

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