CY8C6246BZI-D04 PCB design

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MoPr_4537651
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Hello, 

I am planning on using CY8C6246BZI-D04 as the main MCU for my application. I am planning on using the 80-WLP type. The pitch of this 0.34-0.35 mm (shown below). What is the typical recommended via size for this kind of pitches?

MoPr_4537651_0-1619710953324.png

 

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ncbs
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Hello @MoPr_4537651,

4/10 mil via size can be reduced to 4/8 mil via size.

It is advisable to use via on pad.

 

I would suggest you to contact your FAB house regarding the ease of manufacturability.

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ncbs
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Hi @MoPr_4537651,

CY8C6246BZI-D04 comes in 124-BGA package and not in 80-WLCSP package.
(https://www.cypress.com/file/385916/download --> can be seen in the datasheet)

 

Regards,
Nikhil

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Hi Nikhil,

Thanks for pointing it out. I meant CY8C6247FDI-D02. Space is very critical in our application, so we have to use the smallest package. Would it be feasible to use 3/6 mil or 3.5/7 mil via? Will it be manufacturable easily?

 

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ncbs
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Hi @MoPr_4537651,

It can be recommended to use 0.1mm Drill and 0.25mm Pad micro via. 

Regards,
Nikhil

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Hello Nikhil,

If I use the 4/10 mil via as suggested then the clearance between two adjacent vias will be about 1.7-2 mil. Won't this make the design hard to manufacture? Or is this easier to manufacture compared to having smaller vias such as 3/6 mil?

Thanks & Regards 

Mohan Prabhakar

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ncbs
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500 replies posted 50 likes received 250 sign-ins

Hello @MoPr_4537651,

4/10 mil via size can be reduced to 4/8 mil via size.

It is advisable to use via on pad.

 

I would suggest you to contact your FAB house regarding the ease of manufacturability.

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Thanks for the suggestion! We ended up using 4/8 mil via itself. Unfortunately we had use layer-2 as well for routing which cut off ground references to some of the tracks. Hopefully it will still be functional.

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