CPUSS_DP_CTL register

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KaSi_1722081
Level 1
Level 1

Hello,

The architecture reference manual for PSoC62 outlines the DP_CTL register in the DAP security section, but the register TRM does not detail this register. Could you please provide the relevant documentation?

The section also describes the ability to enable debug access after authentication. Is this a feature available in PSoC62?

Thanks!

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1 Solution
DheerajK_81
Moderator
Moderator
Moderator
First comment on KBA First comment on blog 5 questions asked

I totally agree with you. We should have made the documentation slightly clearer regarding this register. The register CPUSS_DP_CTL is write protected and can only be set by the ROM Boot code or by the user code based on the lifecycle stage.

Hence, this register is not visible in the Register TRM as you cannot access and write into it. Having said that, now how do you enable or disable the APs. Since you cannot change the ROM Boot code for obvious reasons, the only way is by changing the lifecycle stages using the EFUSE bits. Based on the lifecycle stage, the registers EFUSE_DATA_SECURE_ACCESS_RESTRICT0 or EFUSE_DATA_DEAD_ACCESS_RESTRICT0 can be used to set the bits to enable/disable APs as seen in Page#650 of this document: https://www.cypress.com/file/421411/download

Answer to your second question:

When you transition into a SECURE lifecycle stage, you have the choice of enabling/disabling the debug ports using the registers I mentioned above. If you enable debug, it will be possible only after successful authentication of flash boot and application code. You can find more information about this here: https://www.cypress.com/file/447981/download

Regards,
Dheeraj

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2 Replies
PSBU_2325551
Level 4
Level 4
First like received

Hi ,

Please check EFUSE_DATA_SECURE_ACCESS_RESTRICT0 and EFUSE_DATA_DEAD_ACCESS_RESTRICT0 registers, they have bit to enable/disable debug access port

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DheerajK_81
Moderator
Moderator
Moderator
First comment on KBA First comment on blog 5 questions asked

I totally agree with you. We should have made the documentation slightly clearer regarding this register. The register CPUSS_DP_CTL is write protected and can only be set by the ROM Boot code or by the user code based on the lifecycle stage.

Hence, this register is not visible in the Register TRM as you cannot access and write into it. Having said that, now how do you enable or disable the APs. Since you cannot change the ROM Boot code for obvious reasons, the only way is by changing the lifecycle stages using the EFUSE bits. Based on the lifecycle stage, the registers EFUSE_DATA_SECURE_ACCESS_RESTRICT0 or EFUSE_DATA_DEAD_ACCESS_RESTRICT0 can be used to set the bits to enable/disable APs as seen in Page#650 of this document: https://www.cypress.com/file/421411/download

Answer to your second question:

When you transition into a SECURE lifecycle stage, you have the choice of enabling/disabling the debug ports using the registers I mentioned above. If you enable debug, it will be possible only after successful authentication of flash boot and application code. You can find more information about this here: https://www.cypress.com/file/447981/download

Regards,
Dheeraj