ADC 0 setup in CY8CKIT-062S4 kit

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aleung
Level 2
Level 2
10 sign-ins 5 replies posted 5 questions asked

I'm try to set up the ADC using the device configurator, as follow:

- Vref = Internal Reference (from AREF Resource)   1.2V

- No. of channel =2

-Ch0 Vplus= P10.0,  Cho Vminus=AREF vref

-Ch1 Vplus= P10.1,  Cho Vminus=AREF vref

After I set this the Notice list Show:    "Task: ADC clock frequency, 2000000, is out of the supported range (1.7 to 1.8 MHz). [CY8C6244LQI-S4D92: 12-bit SAR ADC 0 [clk_freq_display]]"

Then I try to set the "Clock Select" from "Deep Sleep Clock" to  "Peripheral Clock Divider" ,  and "Clock" as "8 bit Divider 2  clk"   ,  the Clock frequency shows as 1.786MHz  +/- 2.4%.

But the notice list shows Task:      "Resource 'amuxbus_a_sar' is overused between nets 'csd[0].csd[0]:sense:3, pass[0].saradc[0].sar[0]:Vminus:0, pass[0].saradc[0].sar[0]:Vminus:1' [CY8C6244LQI-S4D92: Routing Results]"

How can I solve this?

 

 

 

 

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1 Solution
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi,

Can you try assigning ADC input pins as port 10 pins ? This is the dedicated SARMUX port and do not use AMUXBUS resource to route the signal. Currently in your design Capsense block is already using the resource. Can you check whether changing the pins resolves the issue ?

Best Regards,
Vasanth

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2 Replies
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi,

Can you try assigning ADC input pins as port 10 pins ? This is the dedicated SARMUX port and do not use AMUXBUS resource to route the signal. Currently in your design Capsense block is already using the resource. Can you check whether changing the pins resolves the issue ?

Best Regards,
Vasanth

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aleung
Level 2
Level 2
10 sign-ins 5 replies posted 5 questions asked

Hi,

I do not use the Capsense block on the kit, and I remove the related setting on capsense and it's OK.

Thanks! 

 

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