problem getting UART Interrupts to fire on PSOC6 CM0P and Modus toolbox 2.3 PDL2.2.1

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John_K
Level 4
Level 4
25 replies posted 10 questions asked First like received

I've been trying to make UART interrupts work on the PSOC6 CM0P processor without success; I have been able to get CM4 to work.  This is all on Modus toolbox 2.3, pdl2.2.1, and just using pdl and low level uart apis (no HAL).

I took a simple Cypress PSOC6 UART dma demo project that runs on CM4 and modified it, removing the dma functionality.  For this simple test I am using the Cypress CY8CPROTO-063-BLE board and its debug uart.  The app receives and prints any received char from the terminal, and will make a trivial check for a flag set in the UART ISR. I have arbitrary set multiple tx and rx fifo interrupt conditions to force lots of interrupts.

Debugging in Eclipse IDE, the UART fires in CM4 project, I can break in the ISR, and everything works as expected.

I modified the project for CM0 (following Cypress guides and appnotes) mainly by:

  1. Setting CORE=CM0P in Makefile
  2. Adjusting the linker scripts to increase flash and sram for Cm0 app
  3. Adjusting the interrupt cfg structures for CM0
  4. Assigning (arbitrary) CM0 NVIC Mux 9 for the interrupt cm0pSrc

The app compiles and works on both processors  with regards to echoing received chars to to the terminal. 

On CM4 the interrupt fires,  isr flag is set, and I  break in the ISR routine.

But on CM0P no interrupt fires, no isr flag is set, and I can't break in the ISR.

 

I have attached both projects here for reference.  What am I missing?

 

 

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1 Solution
John_K
Level 4
Level 4
25 replies posted 10 questions asked First like received

I found it.  I transposed the interrupt configuration; in the nvic enable, I was mistakenly enabling the interrupt source (scb source) which is correct  procedure for m4 and not the cm0 interrupt interrupt itself(cm0 nvic mux 9).  

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2 Replies
John_K
Level 4
Level 4
25 replies posted 10 questions asked First like received

I found it.  I transposed the interrupt configuration; in the nvic enable, I was mistakenly enabling the interrupt source (scb source) which is correct  procedure for m4 and not the cm0 interrupt interrupt itself(cm0 nvic mux 9).  

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AlenAn14
Moderator
Moderator
Moderator
500 replies posted 100 solutions authored 250 replies posted

Hi @John_K,

Thank you for sharing this information with the community.

Referring to section 3.2, Configuring Interrupts using PDL, of PSoC 6 MCU Interrupts application note, the configuration for cm0+ interrupts has been specified in detail as highlighted in below figure.

AlenAn14_0-1634622634464.png

 

The "intrSrc" refers to the NVIC MUX incase of CM0+ CPU and the "cm0pSrc" refers to the IRQ number while for CM4 CPU "intrSrc" refers to the IRQ Number and "cm0pSrc" need not be specified for CM4 CPU.

Hope this helps .

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