PSoC™ 6 SDK Forum Discussions

Dear Receiver, 

Could you please help me to get the sample code of  "UART interrupt" based on PSOC 6 ?!

The current kit I used in CY8CPROTO-062-4343W and the IDE I use is Modustoolbox v4.0.

Thank you so much.

Hello,
i'm trying to use the CM0+ Core for BLE. I have chosen the BLE FindMe Example for a starting point and added a custom linkerscript. But as soon as I specify FLASH_CM0P_SIZE above 0x2000 , the resulting executable doesn't run on my CYC8CPROTO-063-BLE.  

Memory Map:

ram (rwx) : ORIGIN = 0x08008000, LENGTH = 0x3F800
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000

I searched a lot on the web and on this site and didn't find an example for using the CM0P_BLESS component.

A complete example on how to set up the CM0P_BLESS component would be very helpful.

Thank you,
 Matthias

Hello Infineon support team.  

We can't seem to get support in the following ways!
In what ways can we support print float var.?

I can only solve it through the following methods at present, but I think there is not a good method!

sprintf(temp, "%ld.", (adc_out / 1000000));
sprintf(stringBuffer, "%ld", (adc_out % 1000000));
strcat(temp, stringBuffer);

printf("%s\r\n", temp);

Dear Sirs and Madams,

We are thinking of migrating from PSoC Creator to ModusToolBox.

However, I've been searching for and reading the ModusToolBox documentation, but I don't know how to use LUT, status register and control register when developing PSoC6 with ModusToolBox.

Do you have materials that describe how to use these?

Or is it recommended to use PSoC Creator?

Regards,

Hello Infineon support team. 

My operating environment:
Win10
ModusToolBox Version: 2.4.0
Eclipse Build ID: 2460
Evk: CY8CKIT-062-WIFI-BT
mtb-hal-cat1 release-v2.0.1

When I define normal pin to ADC pin is fine, but use the CSD pin(CYBSP_CSD_SLD2) then function abnormally.
It seems that the pin is occupied, how can I release it?
I switched to using PDL type to use CYBSP_CSD_SLD2 and it worked fine!

Below is my sample code:

#include "cyhal.h"
#include "cybsp.h"
#include "cy_retarget_io.h"

int main(void)
{
  cy_rslt_t result;
  cyhal_adc_t adc_obj;
  cyhal_adc_channel_t adc_chan_0_obj;

  /* Initialize the device and board peripherals */
  result = cybsp_init() ;
  if (result != CY_RSLT_SUCCESS)
  {
    CY_ASSERT(0);
  }

  __enable_irq();

  cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);

  // ADC conversion result.
  int32_t adc_out;
  cyhal_gpio_free(P8_5);		// CYBSP_CSD_SLD2
  // Initialize ADC. The ADC block which can connect to pin CYBSP_CSD_SLD2 is selected
  result = cyhal_adc_init(&adc_obj, P8_5, NULL);

  // ADC configuration structure
  const cyhal_adc_config_t ADCconfig ={
   .continuous_scanning = true,
   .resolution = 12,
   .average_count = 1,
   .average_mode_flags = 0,
   .ext_vref_mv = 0,
   .vneg = CYHAL_ADC_VNEG_VREF,
   .vref = CYHAL_ADC_REF_VDDA,
   .ext_vref = NC,
   .is_bypassed = false,
   .bypass_pin = NC
  };

  // Call the ADC configure function to begin continuous scanning
  cyhal_adc_configure(&adc_obj, &ADCconfig);

  // Initialize ADC channel, allocate channel number 0 to pin CYBSP_CSD_SLD2 as this is the first
  // channel initialized
  const cyhal_adc_channel_config_t channel_config = { .enable_averaging = false, .min_acquisition_ns = 220, .enabled = true };
  result = cyhal_adc_channel_init_diff(&adc_chan_0_obj, &adc_obj, P8_5, CYHAL_ADC_VNEG, &channel_config);

  for (;;)
  {
    adc_out = cyhal_adc_read_uv(&adc_chan_0_obj);
    printf("%d\r\n", adc_out);
    cyhal_system_delay_ms(100);
  }
}

Hello,

I'm working on a Dual Core Application in ModusToolbox using the CY8CPROTO-062-4343W proto board.  The project is setup so that the CM0P collects data and sends it to the CM4 core.  About 4 KB of data needs to be exchanged every second.

Originally, I thought about sharing a pointer since the physical memory is shared between the two cores.  However, looking at the linker scripts, I see that the logical memory between the cores doesn't overlap, and that makes sense since you can't have the heap allocators on each core overwriting the same physical address.

The IPC Pipes example project only sends 4 bytes of actual data.  I cannot find anything in the datasheets about how much data can be transferred over IPC.  Will this be able to support my required throughput?

Otherwise, is there a way to specify a small region of memory that is shared between the two cores?

Best regards,

Cory

Operating environment:
Win10
ModusToolBox Version: 2.4.0
Eclipse Build ID: 2460
Evk: CY8CKIT-062-WIFI-BT
mtb-hal-cat1 release-v2.0.1

When I use cyhal_pwm_set_duty_cycle to set the duty equal to 0% or 100%, it seems the output is not correct!
result = cyhal_pwm_set_duty_cycle(&pwm_obj, 0.0f, 10000);  ==> Then PWM output is 100%(keep high level output)
result = cyhal_pwm_set_duty_cycle(&pwm_obj, 100.0f, 10000); ==> Then PWM output is 99.98%

I wonder does there is any bugs in the function library cyhal_pwm_set_duty_cycle() & cyhal_pwm_set_period_and_compare().

Below is my sample code:

#include "cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"

float fCompareValue = 0.0f;

int main(void)
{
    cy_rslt_t result;
    cyhal_pwm_t pwm_obj;

    /* Initialize the device and board peripherals */
    result = cybsp_init() ;
    if (result != CY_RSLT_SUCCESS)
    {
        CY_ASSERT(0);
    }

    __enable_irq();
    cyhal_gpio_init(CYBSP_LED9, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, CYBSP_LED_STATE_OFF);

	// Initialize PWM on the supplied pin and assign a new clock
    result = cyhal_pwm_init(&pwm_obj, CYBSP_LED8, NULL);
	// Set a duty cycle of 100% and frequency of 10KHz
    result = cyhal_pwm_set_duty_cycle(&pwm_obj, fCompareValue, 10000);
	// Start the PWM output
    result = cyhal_pwm_start(&pwm_obj);

    for (;;)
    {
		if(fCompareValue <= 100.0f)
		{
			result = cyhal_pwm_set_duty_cycle(&pwm_obj, fCompareValue, 10000);
			cyhal_gpio_toggle(CYBSP_LED9);
			Cy_SysLib_Delay(250);
			fCompareValue += 10.0f;
		}
    }
}

Actually output waveform:

Operating environment:
Win10
ModusToolBox Version: 2.4.0
Eclipse Build ID: 2460
Evk: CY8CKIT-062-WIFI-BT

if I'm using firmware to config the GPIO interrupt edge then doesn't work.
But when I to setting "Interrupt Trigger Type" through Device Configurator then works fine.
May I ask you seniors, what is the cause of this problem?

source code:

#include "cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"

bool bf_LEDStatus = 0;

void Interrupt_Handler_Port0(void)
{
  Cy_GPIO_ClearInterrupt(P0_4_PORT, P0_4_NUM);
  bf_LEDStatus = !bf_LEDStatus;
  Cy_GPIO_Inv(P1_5_PORT, P1_5_NUM);
}

int main(void)
{
  cy_rslt_t result;

 /* Initialize the device and board peripherals */
 result = cybsp_init() ;
 if (result != CY_RSLT_SUCCESS)
 {
    CY_ASSERT(0);
 }

 __enable_irq();

 // Interrupt config structure
 cy_stc_sysint_t intrCfg =
 {
    /*.intrsrc=*/ ioss_interrupts_gpio_0_IRQn, /* Interrupt source is GPIO port 3 interrupt */
    /*.intrPriority =*/ 4UL /* Interrupt priority is 7 */
 };

 /* Initialize the interrupt with vector at Interrupt_Handler_Port3() */
 Cy_SysInt_Init(&intrCfg, &Interrupt_Handler_Port0);
 // Send the button through the glitch filter
 Cy_GPIO_SetFilter(P0_4_PORT, P0_4_NUM);
 // Falling edge interrupt
 Cy_GPIO_SetInterruptEdge(P0_4_PORT, P0_4_NUM, CY_GPIO_INTR_FALLING);
 /* Enable the interrupt */
 NVIC_EnableIRQ(intrCfg.intrSrc);

 for (;;)
 {
 }
}