Using PDL v2.40, and Modus Device Configurator to configure the SAR ADC< there is a bug in the SAR-5.0.cypersonality. (I did a brief check and this issue is also present in previous PDL and SAR personality file versions as well).
According to the PSOC6 TRM, the SAR can be clocked by 1.7 MHz to 18 MHz without an external bypass capacitor. From the TRM:
36.2.1.6 SAR ADC Clock
Note: The maximum SAR ADC clock frequency may be limited to less than 18 MHz by the PSoC 61 datasheet/PSoC 62 datasheet specification for sample rate maximum.
SAR ADC clock frequency must be between 1.8 MHz and 18 MHz, which comes from the peripheral clock (CLK_PERI) in thesystem resources subsystem (SRSS). See the Clocking System chapter on page 237 to know how to configure the peripheral clock.
The PDL 'sar-5.0.cypersonality' file has data validators to check the minimim clock frequency (works) and the maximum (does not work). The device configurator incorrectly shows the valid frequency range as min1.7 MHz and max 1.8 MHz.
Checking the sar-5.0.cypersonality file, the issue is with this line (75):
<ParamString id="clkFreqMaxMHz" name="clkFreqMax" group="Connections" default="`${(vref_byp_cap || (vref_select eq CY_SAR_VREF_SEL_VDDA) || (vref_select eq CY_SAR_VREF_SEL_EXT)) ? ((2000000 == maxSampleRate) ? 36 : 18) : 1.8}`" visible="false" editable="false" desc="Maximum supported ADC clock frequency" />
where the max frequency has a typo : 1.8 MHz instead of 18 MHZ. This issues prevents setting a clock in the valid range, unless the ".bypassed" configuration is selected . It shouldn't have to be bypassed to be clocked in this range.
Looks like an easy fix to address in PDL release.
