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Hi,
I have a problem trying to get high frequencies using the PDM_PCM example. At standard frequencies, it works well, when I modify SAMPLE_RATE_HZ and DECIMATION_RATE I get the desired clock frequencies. The main problem is when I try to configure it with DECIMATION_RATE = 64 and SAMPLE_RATE_HZ 48000 to get a clock frequency of 3.072 MHz. When I analyze with an oscilloscope the signal clock output I only get 2.69MHz clock frequency with a duty cycle of 66.6%, which is quite strange.
Any ideas of how can I get the correct clock frequency?
Solved! Go to Solution.
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To get to 3.072 MHz, you need to make sure the AUDIO_SYS_CLOCK_HZ is multiple of 3.072 MHz, otherwise you will not get a accurate clock. You can set the AUDIO_SYS_CLOCK_HZ at 24.576 MHz.
To have even better accuracy, you can also source the PLL from the ECO.
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Hi,
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Can you try to enable the PLL clock in clock_init() function?
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That's the clock_init function:
void clock_init(void)
{
/* Initialize the PLL */
cyhal_clock_get(&pll_clock, &CYHAL_CLOCK_PLL[0]);
cyhal_clock_init(&pll_clock);
cyhal_clock_set_frequency(&pll_clock, AUDIO_SYS_CLOCK_HZ, NULL);
/* Initialize the audio subsystem clock (HFCLK1) */
cyhal_clock_get(&audio_clock, &CYHAL_CLOCK_HF[1]);
cyhal_clock_init(&audio_clock);
cyhal_clock_set_source(&audio_clock, &pll_clock);
cyhal_clock_set_enabled(&audio_clock, true, true);
}
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Add cyhal_clock_set_enabled(&pll_clock, true, true);
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Adding this line made it works.