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Hi,
TL;DR: How to know the Interrupt number that is triggered when Counter triggers a Compare or TC ?
I'm migrating a project from PSoC Creator (Schematic editor) to ModusToolbox (PDL).
In PSoC Creator's Schematic Editor, I can assign an interrupt (ISR) to the Counter object.
And I can get the number of the Interrupt because it gets autogenerated by the fitter (?).
E.g: If I have an ISR object called "ISR_Counter", then a "#define ISR_Counter__INTC_NUMBER xxx" will be generated.
And I want to know the interrupt number when using PDL or HAL API?
e.g:
// Which NVIC will be triggered ?
cyhal_timer_register_callback(&led_blink_timer, isr_timer, NULL);
Thanks!
Solved! Go to Solution.
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ModusToolbox PSoC 6 SDK
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Hi @ricardoquesada ,
In case you just want to know the NVIC interrupt number, refer to the device.h file.
For PSoC4 - 149 kit the following holds true:
\file cy8c4147azi_s475.h
/*******************************************************************************
* Interrupt Number Definition
*******************************************************************************/
typedef enum {
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* CY8C4147AZI-S475 Peripheral Interrupt Numbers */
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO P0 */
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO P1 */
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO P2 */
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO P3 */
ioss_interrupt_gpio_IRQn = 4, /*!< 4 [DeepSleep] GPIO All Ports */
lpcomp_interrupt_IRQn = 5, /*!< 5 [DeepSleep] LPCOMP trigger interrupt */
srss_interrupt_wdt_IRQn = 6, /*!< 6 [DeepSleep] WDT */
scb_0_interrupt_IRQn = 7, /*!< 7 [DeepSleep] SCB #0 */
scb_1_interrupt_IRQn = 8, /*!< 8 [DeepSleep] SCB #1 */
scb_2_interrupt_IRQn = 9, /*!< 9 [DeepSleep] SCB #2 */
scb_3_interrupt_IRQn = 10, /*!< 10 [DeepSleep] SCB #3 */
scb_4_interrupt_IRQn = 11, /*!< 11 [DeepSleep] SCB #4 */
pass_0_interrupt_ctbs_IRQn = 12, /*!< 12 [DeepSleep] CTBm Interrupt (all CTBms) */
wco_interrupt_IRQn = 13, /*!< 13 [DeepSleep] WCO WDT Interrupt */
cpuss_interrupt_dma_IRQn = 14, /*!< 14 [Active] DMA Interrupt */
cpuss_interrupt_spcif_IRQn = 15, /*!< 15 [Active] SPCIF interrupt */
csd_interrupt_IRQn = 16, /*!< 16 [Active] CSD #0 (Primarily Capsense) */
tcpwm_interrupts_0_IRQn = 17, /*!< 17 [Active] TCPWM #0, Counter #0 */
tcpwm_interrupts_1_IRQn = 18, /*!< 18 [Active] TCPWM #0, Counter #1 */
tcpwm_interrupts_2_IRQn = 19, /*!< 19 [Active] TCPWM #0, Counter #2 */
tcpwm_interrupts_3_IRQn = 20, /*!< 20 [Active] TCPWM #0, Counter #3 */
tcpwm_interrupts_4_IRQn = 21, /*!< 21 [Active] TCPWM #0, Counter #4 */
tcpwm_interrupts_5_IRQn = 22, /*!< 22 [Active] TCPWM #0, Counter #5 */
tcpwm_interrupts_6_IRQn = 23, /*!< 23 [Active] TCPWM #0, Counter #6 */
tcpwm_interrupts_7_IRQn = 24, /*!< 24 [Active] TCPWM #0, Counter #7 */
pass_0_interrupt_sar_IRQn = 25, /*!< 25 [Active] SAR */
can_interrupt_can_IRQn = 26, /*!< 26 [Active] CAN Interrupt */
crypto_interrupt_IRQn = 27, /*!< 27 [Active] Crypto Interrupt */
unconnected_IRQn = 240 /*!< 240 Unconnected */
} IRQn_Type;
In the ISR you can check the status (compare the counter values) and take action accordingly.
Thanks and regards
Sobhit
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Hi @ricardoquesada ,
In case you just want to know the NVIC interrupt number, refer to the device.h file.
For PSoC4 - 149 kit the following holds true:
\file cy8c4147azi_s475.h
/*******************************************************************************
* Interrupt Number Definition
*******************************************************************************/
typedef enum {
/* ARM Cortex-M0+ Core Interrupt Numbers */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* CY8C4147AZI-S475 Peripheral Interrupt Numbers */
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO P0 */
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO P1 */
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO P2 */
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO P3 */
ioss_interrupt_gpio_IRQn = 4, /*!< 4 [DeepSleep] GPIO All Ports */
lpcomp_interrupt_IRQn = 5, /*!< 5 [DeepSleep] LPCOMP trigger interrupt */
srss_interrupt_wdt_IRQn = 6, /*!< 6 [DeepSleep] WDT */
scb_0_interrupt_IRQn = 7, /*!< 7 [DeepSleep] SCB #0 */
scb_1_interrupt_IRQn = 8, /*!< 8 [DeepSleep] SCB #1 */
scb_2_interrupt_IRQn = 9, /*!< 9 [DeepSleep] SCB #2 */
scb_3_interrupt_IRQn = 10, /*!< 10 [DeepSleep] SCB #3 */
scb_4_interrupt_IRQn = 11, /*!< 11 [DeepSleep] SCB #4 */
pass_0_interrupt_ctbs_IRQn = 12, /*!< 12 [DeepSleep] CTBm Interrupt (all CTBms) */
wco_interrupt_IRQn = 13, /*!< 13 [DeepSleep] WCO WDT Interrupt */
cpuss_interrupt_dma_IRQn = 14, /*!< 14 [Active] DMA Interrupt */
cpuss_interrupt_spcif_IRQn = 15, /*!< 15 [Active] SPCIF interrupt */
csd_interrupt_IRQn = 16, /*!< 16 [Active] CSD #0 (Primarily Capsense) */
tcpwm_interrupts_0_IRQn = 17, /*!< 17 [Active] TCPWM #0, Counter #0 */
tcpwm_interrupts_1_IRQn = 18, /*!< 18 [Active] TCPWM #0, Counter #1 */
tcpwm_interrupts_2_IRQn = 19, /*!< 19 [Active] TCPWM #0, Counter #2 */
tcpwm_interrupts_3_IRQn = 20, /*!< 20 [Active] TCPWM #0, Counter #3 */
tcpwm_interrupts_4_IRQn = 21, /*!< 21 [Active] TCPWM #0, Counter #4 */
tcpwm_interrupts_5_IRQn = 22, /*!< 22 [Active] TCPWM #0, Counter #5 */
tcpwm_interrupts_6_IRQn = 23, /*!< 23 [Active] TCPWM #0, Counter #6 */
tcpwm_interrupts_7_IRQn = 24, /*!< 24 [Active] TCPWM #0, Counter #7 */
pass_0_interrupt_sar_IRQn = 25, /*!< 25 [Active] SAR */
can_interrupt_can_IRQn = 26, /*!< 26 [Active] CAN Interrupt */
crypto_interrupt_IRQn = 27, /*!< 27 [Active] Crypto Interrupt */
unconnected_IRQn = 240 /*!< 240 Unconnected */
} IRQn_Type;
In the ISR you can check the status (compare the counter values) and take action accordingly.
Thanks and regards
Sobhit
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Great. So, each counter has a fixed associated interrupt.
Thanks!