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PSoC™ 6 SDK

cvanbeek
Level 3
10 replies posted 10 sign-ins 5 replies posted
Level 3

Hello,

I'm working on a Dual Core Application in ModusToolbox using the CY8CPROTO-062-4343W proto board.  The project is setup so that the CM0P collects data and sends it to the CM4 core.  About 4 KB of data needs to be exchanged every second.

Originally, I thought about sharing a pointer since the physical memory is shared between the two cores.  However, looking at the linker scripts, I see that the logical memory between the cores doesn't overlap, and that makes sense since you can't have the heap allocators on each core overwriting the same physical address.

The IPC Pipes example project only sends 4 bytes of actual data.  I cannot find anything in the datasheets about how much data can be transferred over IPC.  Will this be able to support my required throughput?

Otherwise, is there a way to specify a small region of memory that is shared between the two cores?

Best regards,

Cory

 

1 Solution
AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @cvanbeek ,

You can get more information about how to use the IPC registers for data transfers from the PSoC 62 Architecture TRM .
For your specific requirement, the maximum data that can be held in the IPC_STRUCTx_DATA register is 32 bits, which is 4 bytes as you have mentioned. But you also have the option to pass data more than that by passing a pointer to the location of the data in this register as mentioned in section 6.2.1 as shown in the below image.

AlenAn14_0-1643052224398.png

Hope this helps.

Regards
Alen

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5 Replies
AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @cvanbeek ,

You can get more information about how to use the IPC registers for data transfers from the PSoC 62 Architecture TRM .
For your specific requirement, the maximum data that can be held in the IPC_STRUCTx_DATA register is 32 bits, which is 4 bytes as you have mentioned. But you also have the option to pass data more than that by passing a pointer to the location of the data in this register as mentioned in section 6.2.1 as shown in the below image.

AlenAn14_0-1643052224398.png

Hope this helps.

Regards
Alen

cvanbeek
Level 3
10 replies posted 10 sign-ins 5 replies posted
Level 3

Hi Alen,

I think that makes sense to me and I can implement that.  Just to clarify, the address range in the linker scripts for RAM specifies the addresses that the core can allocate memory for. However, either core is capable of reading or writing to those address locations.  That means I can allocate memory in CM0P, send the pointer to CM4, and CM4 can read it.  Is all of that correct?

Thank you,

Cory

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AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @cvanbeek ,

Yes, I have tried a solution where I used the CM0 CPU to create an array of 10 characters and I passed the address of this array using the IPC data register to the CM4+ CPU which was then able to read out the 10 characters using the received address and display the same on the terminal. using a UART.

Warm Regards
Alen

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cvanbeek
Level 3
10 replies posted 10 sign-ins 5 replies posted
Level 3

Hi Alen,

Perfect!  Thank you for looking into this and your prompt replies.

Best regards,

Cory

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AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @cvanbeek ,

Glad to help 🙂.

Please feel free to post any queries or issues you may have on Infineon products in the community and we will be happy to help.

Warm Regards
Alen