Hello Bragadeesh,
currently it seems that the issue is resolved.
The calculations weren't wrong, but the timings (thanks odissey for pointing me into that direction).
For the issue with the status register: the component has a clock input. I assumed that this input samples the value on the data lines. However, according to component datasheet, this is only true if the data lines are configured as sticky. Otherwise, the read of the register will reflect the value at the time of reading the register. I don't know why reading of some of the register returned a zero value, from datasheet description I expected at least garbage (asynchronous to the design) values because the design should always return a value.
So, for all users running into that problem: if you need to sample the value synchronous to a signal, you've to set the register inputs to sticky.
The other issue with wrong results seemed to be a timing issue from one calculation stage to the next. Inverting the clocks of some components solved this issue. Note: I don't fully understand what went wrong. Timing issues seem to be hard to find. So, for now, I'll try to optimize the used custom components.
As soon as I can provide a stripped down example I'll upload it here. @Cypress: maybe you can also provide example projects showing the pitfalls of such situations.
Regards
