"found invalid term in eqn_main pterm equation" internal error from trivial Verilog

[david-given]

I'm trying to make an address decoder for an 8-bit bus. The Verilog code is extremely simple:

module Decoder (
	output  IRQ,
	inout  [7:0] Data,
	input  [7:0] Address,
	input   IE,
	input   RD
);

wire reading = (Address == 8'h40) & !IE & !RD;
assign Data = reading ? 8'h5a : 8'hff;
assign IRQ = 0;

endmodule

 This compiles. However, if I change that last line to:

assign IRQ = reading;

...then it fails to compile, with the following errors:

Error: plm.M0046: E2557: Found invalid term <main_0> in eqn_main pterm equation <!main_0> for instance <Net_2281_7>.
Warning: plm.M0029: Ignoring undriven net "\Decoder_1:reading\". (App=cydsfit)
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)

These look like they're coming from deep inside the Verilog compiler and don't seem related to anything I'm doing. Ignoring the fact that my code snippet doesn't actually do anything useful, what is wrong here?

[odissey1]

david,

The "inout" line seems suspicious:

inout [7:0] Data.

According to your verilog code, the wire Data is an output, not a tri-state buffer. Try changing it to output.

Do you need the Data to be an in-out bus?

[david-given]

I thought I wanted it to be inout --- this is supposed to be a bidirectional bus interface. I just haven't done any of the input logic. I wanted this line:

assign Data = reading ? 8'h5a : 8'hff;

 ...should really have been 8'hZZ instead of 8'hff, but it looks like Z isn't supported.

However, after doing some playing with bufoes I think I can make the entire problem go away by setting my data pins to both input and output with an output enable signal. My code then becomes this:

module Decoder (
	output [7:0] DataOut,
	output  IRQ,
	output  OE,
	input  [7:0] DataIn,
	input  [7:0] Address,
	input   IE,
	input   RD
);

wire reading = (Address == 8'h40) & !IE & !RD;
assign DataOut = 8'h5a;
assign OE = reading;
assign IRQ = reading;

endmodule

Is this a valid way of doing this? If so, what are bidirectional pins for?

[odissey1]

david,

In order to implement the 'inout' terminal, the Warp Verilog requires instantiation of the tri-state buffer. A copy-paste from the Warp Verilog Reference (rev.D),  par 3.1:

3.1  Tri-state Synthesis

Warp does not synthesize tri-state logic. In order to include tri-state logic in a Verilog module the cy_bufoe must be instantiated. The tri-state output of this module, y, must then be connected to an inout port on the Verilog module. That port can then be connected directly to a bidirectional pin on the device. The feedback signal of the cy_bufoe, yfb, can be used to implement a fully bidirectional interface or can be left floating to implement just a tri-state output.

module ex_tri_state (out1, en, in1);
     inout out1;
     input en;
     input in1;
     cy_bufoe buf_bidi (
          .x(in1), // (input) Value to send out
          .oe(en), // (input) Output Enable
          .y(out1), // (inout) Connect to the bidirectional pin
          .yfb()); // (ouptut) Value on the pin brought back in
endmodule

I am not sure how to make a wide 'inout' bus. The 3-state buffer component (cy_bufoe) has only width of 1. A simple starting point could be creating a simple Verilog component with input and output buses, and creating  a schematic with that component and 8 external cy_bufoe components. Once fully debugged, the bufoes  can be moved into the Verlog code.

[david-given]

Is there any practical difference between an input/output pin with OE enabled, and a bidirectional pin with a bufoe attached?

[odissey1 · Accepted solution]

david,

Attached is a project, which demonstrates simplified 3-state bufoe usage. To make it simple, the top component (InOut8) implemented as a schematic, which uses 8 bufoe and custom Verilog component IOCore8. The IOCore8 is implemented in Verilog and has your custom code.

I believe this is simpler than instantiating all 8 bufoes inside the single Verilog code, with same final result. 

You can find both components in components panel: Community/Digital/InOut8/ 

/odissey1

Figure 1. Project schematic.

Figure 2. The InOut8 component schematic. It includes another custom IOCore8 (verilog code) and 8 external bufoe component.

[odissey1]

Found related KBA on using inout pins in Verilog

Using inout pins in Verilog during Custom Component creation in PSoC Creator